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RE: A new RISC and clockless processor by ghutchis on Dec 23, 2018			ghutchis Posts: 15 Joined: Apr 21, 2004 Last seen: Apr 26, 2024
[q][q]That said, an asynchronous design requires its own process-specific cell library. For synchronous designs this cell library is normally provided for you, for async designs it may be up to the user to construct their own async cells out of the normal gate library.[/q] I am not an electronics engineer so excuse me for not understanding this. Are you saying that "normal" HDL does not provide facility for clockless designs ?? What should be done in a emulator like Verilator in that case ??[/q] What most people would consider normal HDL is HDL for clock-based designs (which, after all, constitute the vast majority of designs). Both Verilog and VHDL can simulation asynchronous designs, however doing so requires using at least nominal delay statements in order to make the simulation proceed. As other posters have noted, Verilog and VHDL are also capable of describing designs which are unsynthesizable and arguably unimplementable. Verilator, however, may not be able to simulate them, as Verilator is a cycle-based simulator -- a simulator made for simulating clock-based designs. Any event-based simulator (VCS, Incisive, Icarus) should be able to simulate asynchronous circuits without a problem. That said, an asynchronous design requires its own process-specific cell library. For synchronous designs this cell library is normally provided for you, for async designs it may be up to the user to construct their own async cells out of the normal gate library. I am not an electronics engineer so excuse me for not understanding this. Are you saying that "normal" HDL does not provide facility for clockless designs ?? What should be done in a emulator like Verilator in that case ?? What most people would consider normal HDL is HDL for clock-based designs (which, after all, constitute the vast majority of designs). Both Verilog and VHDL can simulation asynchronous designs, however doing so requires using at least nominal delay statements in order to make the simulation proceed. As other posters have noted, Verilog and VHDL are also capable of describing designs which are unsynthesizable and arguably unimplementable. Verilator, however, may not be able to simulate them, as Verilator is a cycle-based simulator -- a simulator made for simulating clock-based designs. Any event-based simulator (VCS, Incisive, Icarus) should be able to simulate asynchronous circuits without a problem.

RE: A new RISC and clockless processor by xabiturbe on Dec 23, 2018			xabiturbe Posts: 1 Joined: Dec 6, 2006 Last seen: Dec 23, 2018
Hi all, I find this project idea both timely (with the advent of open-source ISAs like RISC-V) and exciting. I do not have specific experience designing async logic, but ready to learn and help. I guess that all people interested in collaborating on this should try to organise (create a dedicated group/repository, etc). Waiting for news on how to organise and work. Please keep me posted. Thanks Hi all, I find this project idea both timely (with the advent of open-source ISAs like RISC-V) and exciting. I do not have specific experience designing async logic, but ready to learn and help. I guess that all people interested in collaborating on this should try to organise (create a dedicated group/repository, etc). Waiting for news on how to organise and work. Please keep me posted. Thanks

RE: A new RISC and clockless processor by Sameer.Sameer on Dec 24, 2018			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Jul 19, 2023
[q] Yes, we would need to create special HW sub-units. Yes, we can have separate graphics processing core, alongside Special DSP for multimedia to process the Images or videos, or Vice-versa. [/q] Okay. Yes, we would need to create special HW sub-units. Yes, we can have separate graphics processing core, alongside Special DSP for multimedia to process the Images or videos, or Vice-versa. Okay.

RE: A new RISC and clockless processor by Sameer.Sameer on Dec 24, 2018			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Jul 19, 2023
[q]What most people would consider normal HDL is HDL for clock-based designs (which, after all, constitute the vast majority of designs). [/q] Right. [q]Both Verilog and VHDL can simulation asynchronous designs, however doing so requires using at least nominal delay statements in order to make the simulation proceed. [/q] How much time would this delay be ?? [q]As other posters have noted, Verilog and VHDL are also capable of describing designs which are unsynthesizable and arguably unimplementable. [/q] Why so ?? [q] Verilator, however, may not be able to simulate them, as Verilator is a cycle-based simulator -- a simulator made for simulating clock-based designs. Any event-based simulator (VCS, Incisive, Icarus) should be able to simulate asynchronous circuits without a problem. [/q] Okay thanks. What most people would consider normal HDL is HDL for clock-based designs (which, after all, constitute the vast majority of designs). Right. Both Verilog and VHDL can simulation asynchronous designs, however doing so requires using at least nominal delay statements in order to make the simulation proceed. How much time would this delay be ?? As other posters have noted, Verilog and VHDL are also capable of describing designs which are unsynthesizable and arguably unimplementable. Why so ?? Verilator, however, may not be able to simulate them, as Verilator is a cycle-based simulator -- a simulator made for simulating clock-based designs. Any event-based simulator (VCS, Incisive, Icarus) should be able to simulate asynchronous circuits without a problem. Okay thanks.

RE: A new RISC and clockless processor by Sameer.Sameer on Dec 24, 2018			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Jul 19, 2023
[q]Hi all, I find this project idea both timely (with the advent of open-source ISAs like RISC-V) and exciting. I do not have specific experience designing async logic, but ready to learn and help. [/q] You are most welcome, my friend. We will gain expertise as we go along. It is incidental that you mentioned RISC-V. I live in India and five or six implementations of RISC-V ( renamed in India as Shakti ) are being done at the Indian Institute of Technology - Madras ( IIT-M ). But it didn't appeal to me to do what they are already doing. [q] I guess that all people interested in collaborating on this should try to organise (create a dedicated group/repository, etc). Waiting for news on how to organise and work. Please keep me posted. Thanks[/q] That is a good suggestion. Do you know whom to contact on the site for this - creation of a dedicated group and under opencores.org/forum or can't we work in this thread itself ?? Hi all, I find this project idea both timely (with the advent of open-source ISAs like RISC-V) and exciting. I do not have specific experience designing async logic, but ready to learn and help. You are most welcome, my friend. We will gain expertise as we go along. It is incidental that you mentioned RISC-V. I live in India and five or six implementations of RISC-V ( renamed in India as Shakti ) are being done at the Indian Institute of Technology - Madras ( IIT-M ). But it didn't appeal to me to do what they are already doing. I guess that all people interested in collaborating on this should try to organise (create a dedicated group/repository, etc). Waiting for news on how to organise and work. Please keep me posted. Thanks That is a good suggestion. Do you know whom to contact on the site for this - creation of a dedicated group and under opencores.org/forum or can't we work in this thread itself ??

RE: A new RISC and clockless processor by Sameer.Sameer on Dec 24, 2018			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Jul 19, 2023
[q]Due to the historical context of HDL suxh as VHDL and Varilog, they can easily be used to simulate hardware units and systems that cannot be synthesized on real hardware at all. Using a simulation environment such as Verilator, gives you no benefit if you don't close the loop. In this case you close the loop by validating your design elements using a real FPGA tool chain applied to real development hardware. Without a feedback loop like this in your development cycle you are wasting your time time. Not only that, anyone who jumps into this blind alley rush is wasting their time trying to help.[/q] Hi, when you say "feedback loop" what exactly are you referring to ?? A clock ?? Due to the historical context of HDL suxh as VHDL and Varilog, they can easily be used to simulate hardware units and systems that cannot be synthesized on real hardware at all. Using a simulation environment such as Verilator, gives you no benefit if you don't close the loop. In this case you close the loop by validating your design elements using a real FPGA tool chain applied to real development hardware. Without a feedback loop like this in your development cycle you are wasting your time time. Not only that, anyone who jumps into this blind alley rush is wasting their time trying to help. Hi, when you say "feedback loop" what exactly are you referring to ?? A clock ??

RE: A new RISC and clockless processor by Sameer.Sameer on Dec 24, 2018			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Jul 19, 2023
[q]I guess that all people interested in collaborating on this should try to organise (create a dedicated group/repository, etc). Waiting for news on how to organise and work. Please keep me posted. Thanks[/q] Hi, I got the mail id of whom to contact : oc-team@opencores.org Let's wait for a few more members before creating a dedicated group, or do you think we should go for it now ?? I guess that all people interested in collaborating on this should try to organise (create a dedicated group/repository, etc). Waiting for news on how to organise and work. Please keep me posted. Thanks Hi, I got the mail id of whom to contact : oc-team@opencores.org Let's wait for a few more members before creating a dedicated group, or do you think we should go for it now ??

RE: A new RISC and clockless processor by aikijw on Dec 25, 2018			aikijw Posts: 76 Joined: Oct 21, 2011 Last seen: Jul 8, 2023
Since he's not answering... I'll answer... He's just talking about the development cycle... Just disregard his advice... We've been through this before. metaforest has some interesting opinions, and you'll probably find that most of them boil down to reasons NOT to do things... His views on simulation, or the value of a hardware free dev effort, are not widely held... He bills himself as an expert. In my opinion, he is not. Every now and again, you run into people that have a long list of reasons why doing anything they don't understand represents a "waste of time". They've never figured out that the real root of learning is, in fact, doing and failing... They derive no pleasure from experimentation or prototyping. Everything is boiled down into cost vs. benefit. If you'd like an awesome career, doing cool work, avoid these people at all costs. Don't work for them. Don't bring them onto your teams. Maybe let them into your homes, but only if they come bearing really good beer. Just put them in a corner and let them Eeyore their way to retirement. Carry on! :-) (and Happy Holidays to everyone!) [q][q]Due to the historical context of HDL suxh as VHDL and Varilog, they can easily be used to simulate hardware units and systems that cannot be synthesized on real hardware at all. Using a simulation environment such as Verilator, gives you no benefit if you don't close the loop. In this case you close the loop by validating your design elements using a real FPGA tool chain applied to real development hardware. Without a feedback loop like this in your development cycle you are wasting your time time. Not only that, anyone who jumps into this blind alley rush is wasting their time trying to help.[/q] Hi, when you say "feedback loop" what exactly are you referring to ?? A clock ??[/q] Since he's not answering... I'll answer... He's just talking about the development cycle... Just disregard his advice... We've been through this before. metaforest has some interesting opinions, and you'll probably find that most of them boil down to reasons NOT to do things... His views on simulation, or the value of a hardware free dev effort, are not widely held... He bills himself as an expert. In my opinion, he is not. Every now and again, you run into people that have a long list of reasons why doing anything they don't understand represents a "waste of time". They've never figured out that the real root of learning is, in fact, doing and failing... They derive no pleasure from experimentation or prototyping. Everything is boiled down into cost vs. benefit. If you'd like an awesome career, doing cool work, avoid these people at all costs. Don't work for them. Don't bring them onto your teams. Maybe let them into your homes, but only if they come bearing really good beer. Just put them in a corner and let them Eeyore their way to retirement. Carry on! :-) (and Happy Holidays to everyone!) Due to the historical context of HDL suxh as VHDL and Varilog, they can easily be used to simulate hardware units and systems that cannot be synthesized on real hardware at all. Using a simulation environment such as Verilator, gives you no benefit if you don't close the loop. In this case you close the loop by validating your design elements using a real FPGA tool chain applied to real development hardware. Without a feedback loop like this in your development cycle you are wasting your time time. Not only that, anyone who jumps into this blind alley rush is wasting their time trying to help. Hi, when you say "feedback loop" what exactly are you referring to ?? A clock ??

RE: A new RISC and clockless processor by Sameer.Sameer on Dec 25, 2018			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Jul 19, 2023
[q]Since he's not answering... I'll answer... He's just talking about the development cycle... Just disregard his advice... We've been through this before. metaforest has some interesting opinions, and you'll probably find that most of them boil down to reasons NOT to do things... His views on simulation, or the value of a hardware free dev effort, are not widely held... He bills himself as an expert. In my opinion, he is not. Every now and again, you run into people that have a long list of reasons why doing anything they don't understand represents a "waste of time". They've never figured out that the real root of learning is, in fact, doing and failing... They derive no pleasure from experimentation or prototyping. Everything is boiled down into cost vs. benefit. If you'd like an awesome career, doing cool work, avoid these people at all costs. Don't work for them. Don't bring them onto your teams. [/q] I accept your advise. :-) [q] Maybe let them into your homes, but only if they come bearing really good beer. [/q] LOL. [q] Carry on! :-) (and Happy Holidays to everyone!) [/q] Happy holidays to you too and all. :-) Since he's not answering... I'll answer... He's just talking about the development cycle... Just disregard his advice... We've been through this before. metaforest has some interesting opinions, and you'll probably find that most of them boil down to reasons NOT to do things... His views on simulation, or the value of a hardware free dev effort, are not widely held... He bills himself as an expert. In my opinion, he is not. Every now and again, you run into people that have a long list of reasons why doing anything they don't understand represents a "waste of time". They've never figured out that the real root of learning is, in fact, doing and failing... They derive no pleasure from experimentation or prototyping. Everything is boiled down into cost vs. benefit. If you'd like an awesome career, doing cool work, avoid these people at all costs. Don't work for them. Don't bring them onto your teams. I accept your advise. :-) Maybe let them into your homes, but only if they come bearing really good beer. LOL. Carry on! :-) (and Happy Holidays to everyone!) Happy holidays to you too and all. :-)

RE: A new RISC and clockless processor by tgahl7 on Jan 21, 2019			tgahl7 Posts: 1 Joined: Jun 21, 2018 Last seen: May 8, 2019
Hey guys, I'm a grad student working on soft core processor research. I don't know how much time I'll have to commit to this project for the next few months (finishing up my Masters thesis) but I'd love to get involved with this project. Hey guys, I'm a grad student working on soft core processor research. I don't know how much time I'll have to commit to this project for the next few months (finishing up my Masters thesis) but I'd love to get involved with this project.

RE: A new RISC and clockless processor by wtariq2000 on Jan 22, 2019			wtariq2000 Posts: 1 Joined: Jan 7, 2013 Last seen: Dec 17, 2021
Please include my email also if you plan on creating a new group for Asynchronous/Clock-less Processor. Thank you. Regards. Please include my email also if you plan on creating a new group for Asynchronous/Clock-less Processor. Thank you. Regards.

RE: A new RISC and clockless processor by Sameer.Sameer on Jan 22, 2019			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Jul 19, 2023
[q]Hey guys, I'm a grad student working on soft core processor research. I don't know how much time I'll have to commit to this project for the next few months (finishing up my Masters thesis) but I'd love to get involved with this project. [/q] Please check your email. Hey guys, I'm a grad student working on soft core processor research. I don't know how much time I'll have to commit to this project for the next few months (finishing up my Masters thesis) but I'd love to get involved with this project. Please check your email.

RE: A new RISC and clockless processor by gookyi on Jan 22, 2019			gookyi Posts: 1 Joined: Jul 23, 2014 Last seen: Jul 4, 2019
Hello, I am a student working on SoC Designs. I find this project interesting and would like to be a part it. Hello, I am a student working on SoC Designs. I find this project interesting and would like to be a part it.

RE: A new RISC and clockless processor by jdmcmullin on Jan 22, 2019			jdmcmullin Posts: 3 Joined: Feb 11, 2017 Last seen: Mar 21, 2022
Hi, I'm interested in this project and would like to help, but may not be able to devote myself full-time to this. As part of my PhD thesis (20 years ago) I designed a RISC processor (synchronous) whose instruction set was targeted at accelerating the parsing and lexical analysis process. (Even got it referenced by an IBM patent!) Now, having retired I've got the time to update the instruction set/design to fit into a medium sized FPGA (and side-projects such as this). Best regards, John McMullin, PhD Hi, I'm interested in this project and would like to help, but may not be able to devote myself full-time to this. As part of my PhD thesis (20 years ago) I designed a RISC processor (synchronous) whose instruction set was targeted at accelerating the parsing and lexical analysis process. (Even got it referenced by an IBM patent!) Now, having retired I've got the time to update the instruction set/design to fit into a medium sized FPGA (and side-projects such as this). Best regards, John McMullin, PhD

RE: A new RISC and clockless processor by ammar89 on Jan 23, 2019			ammar89 Posts: 1 Joined: Sep 18, 2015 Last seen: Jul 6, 2021
Hey guys, I would like to participate in the project, I have some experience with synchronous digital design, but I am really interested in this project and I am willing to spend time learning how asynchronous digital systems work. Cheers, Ammar Kurd Hey guys, I would like to participate in the project, I have some experience with synchronous digital design, but I am really interested in this project and I am willing to spend time learning how asynchronous digital systems work. Cheers, Ammar Kurd

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