Hello, I have been designing a RISC and clockless based processor since 2010. At present there are just a few instructions and a road map.The design is new from scratch. The OS will also have to be written from scratch.

I welcome anyone to contribute to the project.

The opencores page for my project is ( www.opencores.org/projects/taar ).

Sounds familiar! Only, I've been designing mine since 2015 or so.

Dan

Hello Dan, it was interesting to read about your effort and your aims. I didn't know that such a thing called Verilator exists. Like you, an FPGA is out of my reach presently. :)

As you can see, I am an amateur at processor design. But it will be nice to put together our respective projects.

Hello Sameer,
I am also interested in designing the Processor and OS From scratch.

Hello Vishal, I will take it that you are interested to join my project. Welcome. :)

So you are from India ?? Also, are you an electronics engineer ??

I think the first study that we should do is to understand whether for the graphics/multimedia sub-system ( for compression of multimedia files, decompression and rendering ) :

1. Do we need to create special hardware sub-units ??

2. Or can we allot a separate processor core for the graphics, in which case we can have special processor instructions ??

Let us study this document ( https://www.embedded.com/design/prototyping-and-development/4230425/Add-graphics-without-using-a-dedicated-graphics-controller ).

And then, we need to learn to simulate the processor on Verilator ( https://www.veripool.org/wiki/verilator ) that @dgisselq above has used in his project.

I await your reply.

Forgot this : we also need to decide the I/O devices. I think we should have USB 3.0 as the sole I/O interface on the processor end, and hardware converter interfaces on the other end ( Example - USB to HDMI, USB to Ethernet ).

This word "clockless" is getting to me. What exactly is a "clockless" processor?

Some time ago, someone contacted after building a "clockless" AES encryption algorithm. You can read a summary of the discussion that followed here. (The post went viral on Hacker News too)

Dan

As I understand it "clockless" would mean a processor designed with asynchronous design techniques. There have been several successful asynchronous processors designed, including the AMULET processor which implemented the ARM architecture:
http://apt.cs.manchester.ac.uk/projects/processors/amulet/AMULET3_uP.php

I experimented with this in the past, and went so far as to design an async AES engine:
https://github.com/hutch31/Balsa-AES-Core
I'm not sure the Balsa tools will still compile, they are no longer actively maintained.

Tiempo worked at commercializing an asynchronous compiler, they have gotten some traction in ultra-low power applications:
http://www.tiempo-ic.com/products/acc.html

Wouldn't this make the processor design extremely dependent upon the process technology upon which it was built? Since all the timing would change if you adjusted anything ....

It's actually the opposite... An asynchronous circuit is designed so that it runs as fast as current operating conditions allow. Every path has a built in handshake so that it completes as soon as the handshake is received. The trade-off is that the circuit generally takes more wiring/area than the equivalent clocked circuit, and that the performance of the circuit is not predictable.

That said, an asynchronous design requires its own process-specific cell library. For synchronous designs this cell library is normally provided for you, for async designs it may be up to the user to construct their own async cells out of the normal gate library.

Thanks for the summary. Though I must still say that a "clockless" processor is still viable. I will paraphrase @ghutchis : In clockless processors, there will be a list of instructions, each of which will take their own real time, without being broken down into micro-code and without being interrupted by a instruction clock.

Also, I believe this will allow the implementer to have lot of serial logic in the processor.

I am not an electronics engineer so excuse me for not understanding this. Are you saying that "normal" HDL does not provide facility for clockless designs ?? What should be done in a emulator like Verilator in that case ??

I am from India.

I have a Computer engineering degree.

Yes, we would need to create special HW sub-units.

Yes, we can have separate graphics processing core, alongside Special DSP for multimedia to process the Images or videos, or Vice-versa.

I am from India.

I have a Computer engineering degree.

Yes, we would need to create special HW sub-units.

Yes, we can have separate graphics processing core, alongside Special DSP for multimedia to process the Images or videos, or Vice-versa.

Due to the historical context of HDL suxh as VHDL and Varilog, they can easily be used to simulate hardware units and systems that cannot be synthesized on real hardware at all. Using a simulation environment such as Verilator, gives you no benefit if you don't close the loop. In this case you close the loop by validating your design elements using a real FPGA tool chain applied to real development hardware. Without a feedback loop like this in your development cycle you are wasting your time time. Not only that, anyone who jumps into this blind alley rush is wasting their time trying to help.