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A new RISC and clockless processor

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RE: A new RISC and clockless processor by Sameer.Sameer on Jan 23, 2019			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Oct 25, 2024
wtariq2000, gookyi, jdmcmullin, ammar89 - Please check your email. wtariq2000, gookyi, jdmcmullin, ammar89 - Please check your email.

RE: A new RISC and clockless processor by hno on Mar 12, 2019			hno Posts: 7 Joined: Dec 17, 2012 Last seen: Oct 4, 2021
There is quite many smaller FPGA development/evaluation boards at not too unrealisic prices. You can find a good and up to date overview of the available boards at https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards It is a quite different feeling to see the design running live on an FPGA than purely simulated. This is not to say that simulation is overrated. Simulation is a very important aspect of FPGA development. You do not get nearly the same insight in what is happening when the design is running in the FPGA. Note: I strongly recommend starting with an alternative that do have onboard USB programmer. Makes life less tangled. There is quite many smaller FPGA development/evaluation boards at not too unrealisic prices. You can find a good and up to date overview of the available boards at https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards It is a quite different feeling to see the design running live on an FPGA than purely simulated. This is not to say that simulation is overrated. Simulation is a very important aspect of FPGA development. You do not get nearly the same insight in what is happening when the design is running in the FPGA. Note: I strongly recommend starting with an alternative that do have onboard USB programmer. Makes life less tangled.

RE: A new RISC and clockless processor by Yates1011 on Mar 12, 2019			Yates1011 Posts: 1 Joined: Nov 15, 2018 Last seen: Sep 5, 2021
Hi there, I am currently a student on internship with lots of spare time in the evenings/weekends. If it's not too late, I would like to be a part of this project. Regards, William Yates Hi there, I am currently a student on internship with lots of spare time in the evenings/weekends. If it's not too late, I would like to be a part of this project. Regards, William Yates

RE: A new RISC and clockless processor by Sameer.Sameer on Mar 13, 2019			Sameer.Sameer Posts: 22 Joined: Dec 11, 2017 Last seen: Oct 25, 2024
[q]There is quite many smaller FPGA development/evaluation boards at not too unrealisic prices. You can find a good and up to date overview of the available boards at https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards It is a quite different feeling to see the design running live on an FPGA than purely simulated. This is not to say that simulation is overrated. Simulation is a very important aspect of FPGA development. You do not get nearly the same insight in what is happening when the design is running in the FPGA. Note: I strongly recommend starting with an alternative that do have onboard USB programmer. Makes life less tangled.[/q] Thanks for the info, hno ( Are you Joel ?? ). The problem with the Taar project is that it being a new-from-scratch project, there is no point of reference with an existing processor and therefore I don't know how many gates/cells/LUTs I must have in a FPGA for Taar. Also, I am more a designer than an engineer. There is quite many smaller FPGA development/evaluation boards at not too unrealisic prices. You can find a good and up to date overview of the available boards at https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards It is a quite different feeling to see the design running live on an FPGA than purely simulated. This is not to say that simulation is overrated. Simulation is a very important aspect of FPGA development. You do not get nearly the same insight in what is happening when the design is running in the FPGA. Note: I strongly recommend starting with an alternative that do have onboard USB programmer. Makes life less tangled. Thanks for the info, hno ( Are you Joel ?? ). The problem with the Taar project is that it being a new-from-scratch project, there is no point of reference with an existing processor and therefore I don't know how many gates/cells/LUTs I must have in a FPGA for Taar. Also, I am more a designer than an engineer.

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