The error is not shown in the code.please confirm me whether i did right or
not?
and the code is working on modelsim simulator.its shows errors only during
synthesis.

Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5928455 Sent from the OpenCores - IP Cores forum at Nabble.com.

If you don't explain the error we cannot help you.



Than copy & paste the synthesis error so we can help you.

Martin

Hello
I am uploading the code which I changed.I removed mem_sc_if block because I
need only io interface.I also modified scio and added sc2wb into that.There
is no error in the synthesis,however the simulation is not showing any
results.Please help me out if there are any modifications required.
waiting for your reply,
Thanks
Cheers
Tan






Martin Schoeberl wrote:
http://www.nabble.com/user-files/235774/jop-top.vhd jop-top.vhd http://www.nabble.com/user-files/235775/modified-scio.vhd modified-scio.vhd -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5996882 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hi martin
here i attached the code and images which are generated after the modified
program.
can you please advice me what to do..
synthesis is done.but the problem is with simulation.
waiting for your reply
Thanks
Tan

Martin Schoeberl wrote:
http://www.nabble.com/user-files/235774/jop-top.vhd jop-top.vhd http://www.nabble.com/user-files/235775/modified-scio.vhd modified-scio.vhd http://www.nabble.com/user-files/235776/top.jpeg http://www.nabble.com/user-files/235777/top2.jpg -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5997036 Sent from the OpenCores - IP Cores forum at Nabble.com.

Where do you 'upload' your code?
Why did you remove mem_sc_if? You need a main memory for JOP
and this memory is attached by mem_sc_if.

Martin

Martin Schoeberl wrote:
http://www.nabble.com/user-files/235774/jop-top.vhd jop-top.vhd http://www.nabble.com/user-files/235775/modified-scio.vhd modified-scio.vhd -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5997377 Sent from the OpenCores - IP Cores forum at Nabble.com.

I have uploaded generated blocks and also the code.
please let me know if modifications are needed.
thanks
Cheers
tan

Tan wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5997406 Sent from the OpenCores - IP Cores forum at Nabble.com.

Here is another program with sc_mem_if.vhd block.Both the code which I sent
you got synthesised but not showing results when the data is passe through
input pin(wr_data).
can you please tell me where the data should be forced to.Is it from
"wr_data" pin???
cheers
tan

Tan wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5997445 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hi Tan,

attaching files is useless in this group as there are
no attachments allowed - which is good BTW!

wr_data is not a 'pin' it's a 32-bit data connection. For a description of the SimpCon interface see: http://www.opencores.org/projects.cgi/web/simpcon/overview Martin

Hi martin,
Can you give me your mail id so that I can send my code.
BTW I didnot understand what you said.
Cheers
Tan

Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5997640 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hi Tan,

there is some communication issue between you and me: I ask
you questions to get down to the real problem, but you
are not giving me an answer. Perhaps there is a more
fundamental issue than just getting JOP work with
an Wishbone attached IO device.



I'm not sure if I want to get spammed with images and
code fragments. BTW: my time is limited and I canot be
your debugger ;-)



Have you looked into the document I sent you the
link? If yes, than you're quite fast with the
reading...

Martin

Hi
Sorry If I am bothering you too much.Actually I am stuck in my project so
posted the question.
Yeah I will go through the document.Thanks for your immediate response.
cheers
Tan

Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5997821 Sent from the OpenCores - IP Cores forum at Nabble.com.

Martin

I am extremely sorry for being such a pain. The thing is I am stuck in my
project work with my deadline
just a couple of days away.With the issue refusing to budge and with no
alternative in sight, my communication too had turned incoherent. I hope you
understand.


I'm not sure if I want to get spammed with images and code fragments. BTW:
my time is limited and I canot be your debugger ;-)

That was not my intention Martin. I had to resort to asking you to have a
look at my code as I had no other option and I was unable to clearly explain
my problem. I thought showing you my code would give you an idea of the
problem.


quite fast with the
reading...

:-) Trust me Martin, I have indeed read the document. Infact I read it a
week back. As I am working on Simpcon, I downloaded the pdf from
opencores.org. Infact I am quite sure that the answer to my problem is
explained under the Examples section of the document (Section 4). However it
could be because I am a newbie that I havent clearly understood that
section. My colleagues who help me with this have read it as well but they
havent grasped it either.Some more projects and I am sure I will be in a
better position to understand and then hopefully I shall stop being a pest.
Till then I have no other option but to seek your help. Please do
understand.

As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you
remember you had once advised me to change the scio_dspio.vhd. I had changed
it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd
had a counter,a UART, a usb and sc2wb. Since I wanted to use only sc2wb, I
disabled the UART and the USB blocks.

I am pasting the modified code below:
-- SimpCon Wishbone bridge
cmp_wb: entity work.sc2wb generic map (
addr_bits => SLAVE_ADDR_BITS
)
port map(
clk => clk,
reset => reset,
address => address(SLAVE_ADDR_BITS-1 downto 0),
wr_data => wr_data,
rd => sc_rd(1),
wr => sc_wr(1),
rd_data => sc_dout(1),
rdy_cnt => sc_rdy_cnt(1),
wb_out => wb_out,
wb_in => wb_in );

I have also disabled the ser_txd pin in the top module(as I am not using
UArt). In its place I have defined the ports of sc2wb and I2S in the top
module.(as I am interfacing JOP to I2S my input has to go through JOp and
the output has to come from I2S)

Code pasted below:

port (
clk : in std_logic;
rd_data :in std_logic_vector(31 downto 0);

--wr_data:out std_logic_vector(31 downto 0);

sc_rd_data : inout std_logic_vector(31 downto 0);
sc_wr_data : inout std_logic_vector(31 downto 0);


--- watchdog
--
wd : out std_logic;


tx_i2s_sck : out std_logic;
tx_i2s_sd : out std_logic;
tx_i2s_ws : out std_logic;
tx_i2s_int :out std_logic;


--
-- two ram banks
--
ram_addr : out std_logic_vector(17 downto 0);
ram_nwe : out std_logic;
ram_noe : out std_logic;
rama_d : inout std_logic_vector(15 downto 0);
rama_ncs : out std_logic;
rama_nlb : out std_logic;
rama_nub : out std_logic;
ramb_d : inout std_logic_vector(15 downto 0);
ramb_ncs : out std_logic;
ramb_nlb : out std_logic;
ramb_nub : out std_logic
);
end jop;

This is the top module entity.The synthesis works fine but during
simulation,when I force the value to wr_data,there is no respone from
tx_i2s_sd. Do you see anything obviously wrong in what I have done?
Also if there are any questions for which you need answers to help me with
this, do let me know.


Thanks...Tan

p.s. The 'fatal error' that I had mentioned the other day has now been
corrected. It probably was because many slaves were connected to the master.
aND the Xilinx version I am using does not like it.After disabling the UART
and USB components, the problem disappeared.






Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6006363 Sent from the OpenCores - IP Cores forum at Nabble.com.

This is in continuation to the previous mail,I am pasting the top-scio's
entity


entity scio is
generic (addr_bits : integer);

port (
clk : in std_logic;
reset : in std_logic;

-- SimpCon interface

address : in std_logic_vector(addr_bits-1 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd, wr : in std_logic;
rd_data : out std_logic_vector(31 downto 0);
rdy_cnt : out unsigned(1 downto 0);

-- interrupt

irq : out std_logic;
irq_ena : out std_logic;

-- exception

exc_req : in exception_type;
exc_int : out std_logic;





-- serial interface

-- txd : out std_logic;
-- rxd : in std_logic;
-- ncts : in std_logic;

-- watch dog

wd : out std_logic;

-- core i/o pins
l : inout std_logic_vector(20 downto 1);
r : inout std_logic_vector(20 downto 1);
t : inout std_logic_vector(6 downto 1);
b : inout std_logic_vector(10 downto 1);


tx_i2s_sck : out std_logic;
tx_i2s_sd : out std_logic;
tx_i2s_ws : out std_logic;
tx_i2s_int : out std_logic




);
end scio;






Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6006490 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hi Tan,



You could upload your code to a website and provde a link to it
in the posting. That's a less intrusive way ;-)



Do you want to run your design in hardware (FPGA) or just in
a ModelSim simulation?

If you want to run it in an FPGA you need the UART. How would
you download the Java program without a communication path
between your PC and JOP?

Even in the ModelSim simulation the UART makes sense. You
can debug your Java program with print outs. System.out.println()
goes to the UART.

So, there is no reason to remove the UART from the design.



looks ok, that's the same as in scio_dspio.vhd.



looks, like you are only using transmit. No receive
port, right?



Yes, this is the main issue.

Think about a processor (JOP is a processor). When you force just
a value on the data bus, where the processor usually reads instructions
and reads and writes values. What you you think what the processor
will do?

JOP (and each processor) will do nothing usefull without a program!
So you have to write your application (for JOP in Java) and download
it to the RAM.

Start with a simple 'Hello World' and run this in the simulation
or on the real hardware. Use the unmodified code first!!!

Than add your I2S interface and see if 'Hello World' still
runns.

That's my way to perform changes to a unknown project. First
get it unmodified running THAN apply the changes. I do this
even when I'm working with JOP - first a clean, working
strating point.

Cheers,
Martin