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Regarding JOP by Tan on Aug 27, 2006			Tan Posts: 25 Joined: Sep 25, 2010 Last seen: Sep 27, 2010
Thanks Martin. [q]You could upload your code to a website and provde a link to it in the posting. That's a less intrusive way ;-)[/q] Alright Martin. I shall do this henceforth. [q]Do you want to run your design in hardware (FPGA) or just in a ModelSim simulation?[/q] Both. So I would need to have UART enabled. [q]If you want to run it in an FPGA you need the UART. How would you download the Java program without a communication path between your PC and JOP?[/q] [q]Even in the ModelSim simulation the UART makes sense. You can debug your Java program with print outs. System.out.println() goes to the UART.[/q] [q]So, there is no reason to remove the UART from the design.[/q] Got it ! I shall rectify this. [q]looks, like you are only using transmit. No receive port, right?[/q] Yes thats how it is. [q]JOP (and each processor) will do nothing usefull without a program! So you have to write your application (for JOP in Java) and download it to the RAM.[/q] Cheers Martin. I shall do this tomorrow and revert to you with my results (and new queries if any :-) ) Thanks again...Tan. p.s I have acknowledged all your help in the introduction of my Project thesis work. I shall be uploading it to opencores.org after my launch and presentation scheduled on the 1st of Sept. Martin Schoeberl wrote: [q] Hi Tan, [q] That was not my intention Martin. I had to resort to asking you to have a look at my code as I had no other option and I was unable to clearly explain my problem. I thought showing you my code would give you an idea of the problem.[/q] You could upload your code to a website and provde a link to it in the posting. That's a less intrusive way ;-) [q] As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you remember you had once advised me to change the scio_dspio.vhd. I had changed it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd had a counter,a UART, a usb and sc2wb. Since I wanted to use only sc2wb, I disabled the UART and the USB blocks.[/q] Do you want to run your design in hardware (FPGA) or just in a ModelSim simulation? If you want to run it in an FPGA you need the UART. How would you download the Java program without a communication path between your PC and JOP? Even in the ModelSim simulation the UART makes sense. You can debug your Java program with print outs. System.out.println() goes to the UART. So, there is no reason to remove the UART from the design. [q] I am pasting the modified code below: -- SimpCon Wishbone bridge cmp_wb: entity work.sc2wb generic map ( addr_bits => SLAVE_ADDR_BITS ) port map( clk => clk, reset => reset, address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), rdy_cnt => sc_rdy_cnt(1), wb_out => wb_out, wb_in => wb_in );[/q] looks ok, that's the same as in scio_dspio.vhd. [q] tx_i2s_sck : out std_logic; tx_i2s_sd : out std_logic; tx_i2s_ws : out std_logic; tx_i2s_int :out std_logic;[/q] looks, like you are only using transmit. No receive port, right? [q] This is the top module entity.The synthesis works fine but during simulation,when I force the value to wr_data,there is no respone from tx_i2s_sd. Do you see anything obviously wrong in what I have done?[/q] Yes, this is the main issue. Think about a processor (JOP is a processor). When you force just a value on the data bus, where the processor usually reads instructions and reads and writes values. What you you think what the processor will do? JOP (and each processor) will do nothing usefull without a program! So you have to write your application (for JOP in Java) and download it to the RAM. Start with a simple 'Hello World' and run this in the simulation or on the real hardware. Use the unmodified code first!!! Than add your I2S interface and see if 'Hello World' still runns. That's my way to perform changes to a unknown project. First get it unmodified running THAN apply the changes. I do this even when I'm working with JOP - first a clean, working strating point. Cheers, Martin _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -- View this message in context: <A HREF="http://www.nabble.com/Regarding-JOP-tf2059840.html#a6007672">http://www.nabble.com/Regarding-JOP-tf2059840.html#a6007672</A> Sent from the OpenCores - IP Cores forum at Nabble.com. Thanks Martin. You could upload your code to a website and provde a link to it in the posting. That's a less intrusive way ;-) Alright Martin. I shall do this henceforth. Do you want to run your design in hardware (FPGA) or just in a ModelSim simulation? Both. So I would need to have UART enabled. If you want to run it in an FPGA you need the UART. How would you download the Java program without a communication path between your PC and JOP? Even in the ModelSim simulation the UART makes sense. You can debug your Java program with print outs. System.out.println() goes to the UART. So, there is no reason to remove the UART from the design. Got it ! I shall rectify this. looks, like you are only using transmit. No receive port, right? Yes thats how it is. JOP (and each processor) will do nothing usefull without a program! So you have to write your application (for JOP in Java) and download it to the RAM. Cheers Martin. I shall do this tomorrow and revert to you with my results (and new queries if any :-) ) Thanks again...Tan. p.s I have acknowledged all your help in the introduction of my Project thesis work. I shall be uploading it to opencores.org after my launch and presentation scheduled on the 1st of Sept. Martin Schoeberl wrote: Hi Tan, That was not my intention Martin. I had to resort to asking you to have a look at my code as I had no other option and I was unable to clearly explain my problem. I thought showing you my code would give you an idea of the problem. You could upload your code to a website and provde a link to it in the posting. That's a less intrusive way ;-) As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you remember you had once advised me to change the scio_dspio.vhd. I had changed it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd had a counter,a UART, a usb and sc2wb. Since I wanted to use only sc2wb, I disabled the UART and the USB blocks. Do you want to run your design in hardware (FPGA) or just in a ModelSim simulation? If you want to run it in an FPGA you need the UART. How would you download the Java program without a communication path between your PC and JOP? Even in the ModelSim simulation the UART makes sense. You can debug your Java program with print outs. System.out.println() goes to the UART. So, there is no reason to remove the UART from the design. I am pasting the modified code below: -- SimpCon Wishbone bridge cmp_wb: entity work.sc2wb generic map ( addr_bits => SLAVE_ADDR_BITS ) port map( clk => clk, reset => reset, address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), rdy_cnt => sc_rdy_cnt(1), wb_out => wb_out, wb_in => wb_in ); looks ok, that's the same as in scio_dspio.vhd. tx_i2s_sck : out std_logic; tx_i2s_sd : out std_logic; tx_i2s_ws : out std_logic; tx_i2s_int :out std_logic; looks, like you are only using transmit. No receive port, right? This is the top module entity.The synthesis works fine but during simulation,when I force the value to wr_data,there is no respone from tx_i2s_sd. Do you see anything obviously wrong in what I have done? Yes, this is the main issue. Think about a processor (JOP is a processor). When you force just a value on the data bus, where the processor usually reads instructions and reads and writes values. What you you think what the processor will do? JOP (and each processor) will do nothing usefull without a program! So you have to write your application (for JOP in Java) and download it to the RAM. Start with a simple 'Hello World' and run this in the simulation or on the real hardware. Use the unmodified code first!!! Than add your I2S interface and see if 'Hello World' still runns. That's my way to perform changes to a unknown project. First get it unmodified running THAN apply the changes. I do this even when I'm working with JOP - first a clean, working strating point. Cheers, Martin _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6007672 Sent from the OpenCores - IP Cores forum at Nabble.com.

Regarding JOP by Tan on Aug 28, 2006			Tan Posts: 25 Joined: Sep 25, 2010 Last seen: Sep 27, 2010
Hi Martin, I am here with new questions :). As per our disussion yesterday,I used jopsim,after that I gave "doit test test Helloworld",when i tried to simulate "sim" command and found the result positive. Now when i tried the modified scio block which inludes sc2wb in it,it is giving the error at the end in scio block. Below I am pasting the part of simulation result when executed on DOS. Can you please tell me how to include the work library of sc2wb and i2S for simulation.. . C:\newjop\jop\modelsim>sim C:\newjop\jop\modelsim>set jopdir=../vhdl C:\newjop\jop\modelsim>rem set options=-93 -quiet -check_synthesis -lint -pedant icerrors C:\newjop\jop\modelsim>set options=-93 -quiet C:\newjop\jop\modelsim>rmdir /S/Q work The system cannot find the file specified. C:\newjop\jop\modelsim>vlib work C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_jop_config_100.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jop_types.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_ram.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_pll.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_jbc.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_rom.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_memory.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/fifo.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/sc_uart.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_sc_uart.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/wishbone/wb_pack.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/wishbone/wb_test_slave.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/wishbone/wb_top.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/jtbl.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/offtbl.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/cache.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/sc_sram32_flash.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/mem_sc.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/mul.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/extension.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/bcfetch.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/fetch.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/decode.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/shift.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/stack.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/core.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/sc_cnt.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd Error: (vcom-11) Could not find work.sc2wb. Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded name: 'work.sc2wb'. Error: ../vhdl/scio/scio_min.vhd(266): Unknown record element "sc2wb". Error: ../vhdl/scio/scio_min.vhd(287): Statement cannot be labeled. Error: ../vhdl/scio/scio_min.vhd(364): VHDL Compiler exiting C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jopcyc.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/tb_jop.vhd C:\newjop\jop\modelsim>pause Start simulation? Press any key to continue . . . C:\newjop\jop\modelsim>vsim -do sim.do tb_jop Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl C:\newjop\jop\modelsim>cd .. C:\newjop\jop> Martin Schoeberl wrote: [q] Hi Tan, [q] That was not my intention Martin. I had to resort to asking you to have a look at my code as I had no other option and I was unable to clearly explain my problem. I thought showing you my code would give you an idea of the problem.[/q] You could upload your code to a website and provde a link to it in the posting. That's a less intrusive way ;-) [q] As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you remember you had once advised me to change the scio_dspio.vhd. I had changed it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd had a counter,a UART, a usb and sc2wb. Since I wanted to use only sc2wb, I disabled the UART and the USB blocks.[/q] Do you want to run your design in hardware (FPGA) or just in a ModelSim simulation? If you want to run it in an FPGA you need the UART. How would you download the Java program without a communication path between your PC and JOP? Even in the ModelSim simulation the UART makes sense. You can debug your Java program with print outs. System.out.println() goes to the UART. So, there is no reason to remove the UART from the design. [q] I am pasting the modified code below: -- SimpCon Wishbone bridge cmp_wb: entity work.sc2wb generic map ( addr_bits => SLAVE_ADDR_BITS ) port map( clk => clk, reset => reset, address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), rdy_cnt => sc_rdy_cnt(1), wb_out => wb_out, wb_in => wb_in );[/q] looks ok, that's the same as in scio_dspio.vhd. [q] tx_i2s_sck : out std_logic; tx_i2s_sd : out std_logic; tx_i2s_ws : out std_logic; tx_i2s_int :out std_logic;[/q] looks, like you are only using transmit. No receive port, right? [q] This is the top module entity.The synthesis works fine but during simulation,when I force the value to wr_data,there is no respone from tx_i2s_sd. Do you see anything obviously wrong in what I have done?[/q] Yes, this is the main issue. Think about a processor (JOP is a processor). When you force just a value on the data bus, where the processor usually reads instructions and reads and writes values. What you you think what the processor will do? JOP (and each processor) will do nothing usefull without a program! So you have to write your application (for JOP in Java) and download it to the RAM. Start with a simple 'Hello World' and run this in the simulation or on the real hardware. Use the unmodified code first!!! Than add your I2S interface and see if 'Hello World' still runns. That's my way to perform changes to a unknown project. First get it unmodified running THAN apply the changes. I do this even when I'm working with JOP - first a clean, working strating point. Cheers, Martin _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -- View this message in context: <A HREF="http://www.nabble.com/Regarding-JOP-tf2059840.html#a6017103">http://www.nabble.com/Regarding-JOP-tf2059840.html#a6017103</A> Sent from the OpenCores - IP Cores forum at Nabble.com. Hi Martin, I am here with new questions :). As per our disussion yesterday,I used jopsim,after that I gave "doit test test Helloworld",when i tried to simulate "sim" command and found the result positive. Now when i tried the modified scio block which inludes sc2wb in it,it is giving the error at the end in scio block. Below I am pasting the part of simulation result when executed on DOS. Can you please tell me how to include the work library of sc2wb and i2S for simulation.. . C:\newjop\jop\modelsim>sim C:\newjop\jop\modelsim>set jopdir=../vhdl C:\newjop\jop\modelsim>rem set options=-93 -quiet -check_synthesis -lint -pedant icerrors C:\newjop\jop\modelsim>set options=-93 -quiet C:\newjop\jop\modelsim>rmdir /S/Q work The system cannot find the file specified. C:\newjop\jop\modelsim>vlib work C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_jop_config_100.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jop_types.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_ram.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_pll.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_jbc.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_rom.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_memory.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/fifo.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/sc_uart.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_sc_uart.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/wishbone/wb_pack.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/wishbone/wb_test_slave.vhd C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/wishbone/wb_top.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/jtbl.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/offtbl.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/cache.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/sc_sram32_flash.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/mem_sc.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/mul.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/extension.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/bcfetch.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/fetch.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/decode.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/shift.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/stack.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/core.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/sc_cnt.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd Error: (vcom-11) Could not find work.sc2wb. Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded name: 'work.sc2wb'. Error: ../vhdl/scio/scio_min.vhd(266): Unknown record element "sc2wb". Error: ../vhdl/scio/scio_min.vhd(287): Statement cannot be labeled. Error: ../vhdl/scio/scio_min.vhd(364): VHDL Compiler exiting C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jopcyc.vhd C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/tb_jop.vhd C:\newjop\jop\modelsim>pause Start simulation? Press any key to continue . . . C:\newjop\jop\modelsim>vsim -do sim.do tb_jop Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl C:\newjop\jop\modelsim>cd .. C:\newjop\jop> Martin Schoeberl wrote: Hi Tan, That was not my intention Martin. I had to resort to asking you to have a look at my code as I had no other option and I was unable to clearly explain my problem. I thought showing you my code would give you an idea of the problem. You could upload your code to a website and provde a link to it in the posting. That's a less intrusive way ;-) As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you remember you had once advised me to change the scio_dspio.vhd. I had changed it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd had a counter,a UART, a usb and sc2wb. Since I wanted to use only sc2wb, I disabled the UART and the USB blocks. Do you want to run your design in hardware (FPGA) or just in a ModelSim simulation? If you want to run it in an FPGA you need the UART. How would you download the Java program without a communication path between your PC and JOP? Even in the ModelSim simulation the UART makes sense. You can debug your Java program with print outs. System.out.println() goes to the UART. So, there is no reason to remove the UART from the design. I am pasting the modified code below: -- SimpCon Wishbone bridge cmp_wb: entity work.sc2wb generic map ( addr_bits => SLAVE_ADDR_BITS ) port map( clk => clk, reset => reset, address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), rdy_cnt => sc_rdy_cnt(1), wb_out => wb_out, wb_in => wb_in ); looks ok, that's the same as in scio_dspio.vhd. tx_i2s_sck : out std_logic; tx_i2s_sd : out std_logic; tx_i2s_ws : out std_logic; tx_i2s_int :out std_logic; looks, like you are only using transmit. No receive port, right? This is the top module entity.The synthesis works fine but during simulation,when I force the value to wr_data,there is no respone from tx_i2s_sd. Do you see anything obviously wrong in what I have done? Yes, this is the main issue. Think about a processor (JOP is a processor). When you force just a value on the data bus, where the processor usually reads instructions and reads and writes values. What you you think what the processor will do? JOP (and each processor) will do nothing usefull without a program! So you have to write your application (for JOP in Java) and download it to the RAM. Start with a simple 'Hello World' and run this in the simulation or on the real hardware. Use the unmodified code first!!! Than add your I2S interface and see if 'Hello World' still runns. That's my way to perform changes to a unknown project. First get it unmodified running THAN apply the changes. I do this even when I'm working with JOP - first a clean, working strating point. Cheers, Martin _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6017103 Sent from the OpenCores - IP Cores forum at Nabble.com.

Regarding JOP by Unknown on Aug 28, 2006			Not available!
[q] As per our disussion yesterday,I used jopsim,after that I gave "doit test test Helloworld",when i tried to simulate "sim" command and found the result positive.[/q] ok, fine. [q] Now when i tried the modified scio block which inludes sc2wb in it,it is giving the error at the end in scio block. Below I am pasting the part of simulation result when executed on DOS. Can you please tell me how to include the work library of sc2wb and i2S for simulation..[/q] [q] C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd Error: (vcom-11) Could not find work.sc2wb. Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded name: 'work.sc2wb'.[/q] You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. Martin As per our disussion yesterday,I used jopsim,after that I gave "doit test test Helloworld",when i tried to simulate "sim" command and found the result positive. ok, fine. Now when i tried the modified scio block which inludes sc2wb in it,it is giving the error at the end in scio block. Below I am pasting the part of simulation result when executed on DOS. Can you please tell me how to include the work library of sc2wb and i2S for simulation.. C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd Error: (vcom-11) Could not find work.sc2wb. Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded name: 'work.sc2wb'. You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. Martin

Regarding JOP by Tan on Aug 28, 2006			Tan Posts: 25 Joined: Sep 25, 2010 Last seen: Sep 27, 2010
Hi Martin, [q]You have to add your design file to the ModelSim project. [q]That means: add it to the sim.bat in the modelsim directory. [/q] How to include the design file into sim.bat???Can you please explain in detail.. I tried it but couldnot get any idea how to do that.. cheers tan Martin Schoeberl wrote: [q] [q] As per our disussion yesterday,I used jopsim,after that I gave "doit test test Helloworld",when i tried to simulate "sim" command and found the result positive.[/q] ok, fine. [q] Now when i tried the modified scio block which inludes sc2wb in it,it is giving the error at the end in scio block. Below I am pasting the part of simulation result when executed on DOS. Can you please tell me how to include the work library of sc2wb and i2S for simulation..[/q] [q] C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd Error: (vcom-11) Could not find work.sc2wb. Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded name: 'work.sc2wb'.[/q] You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. Martin _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -- View this message in context: <A HREF="http://www.nabble.com/Regarding-JOP-tf2059840.html#a6018021">http://www.nabble.com/Regarding-JOP-tf2059840.html#a6018021</A> Sent from the OpenCores - IP Cores forum at Nabble.com. Hi Martin, You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. How to include the design file into sim.bat???Can you please explain in detail.. I tried it but couldnot get any idea how to do that.. cheers tan Martin Schoeberl wrote: As per our disussion yesterday,I used jopsim,after that I gave "doit test test Helloworld",when i tried to simulate "sim" command and found the result positive. ok, fine. Now when i tried the modified scio block which inludes sc2wb in it,it is giving the error at the end in scio block. Below I am pasting the part of simulation result when executed on DOS. Can you please tell me how to include the work library of sc2wb and i2S for simulation.. C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd Error: (vcom-11) Could not find work.sc2wb. Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded name: 'work.sc2wb'. You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. Martin _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6018021 Sent from the OpenCores - IP Cores forum at Nabble.com.

Regarding JOP by Unknown on Aug 28, 2006			Not available!
[q]You have to add your design file to the ModelSim project. [q]That means: add it to the sim.bat in the modelsim directory. [/q] How to include the design file into sim.bat???Can you please explain in detail..[/q] What about using a text editor and open sim.bat??? [q] I tried it but couldnot get any idea how to do that..[/q] Add your VHDL files in the same way as the other files are listed. You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. How to include the design file into sim.bat???Can you please explain in detail.. What about using a text editor and open sim.bat??? I tried it but couldnot get any idea how to do that.. Add your VHDL files in the same way as the other files are listed.

Regarding JOP by Tan on Aug 28, 2006			Tan Posts: 25 Joined: Sep 25, 2010 Last seen: Sep 27, 2010
Hi martin, I got it... I just right clicked the sim.bat and went to edit and modified it accordingly... thanks so much for your help.. Tan Martin Schoeberl wrote: [q] [q]You have to add your design file to the ModelSim project. [q]That means: add it to the sim.bat in the modelsim directory. [/q] How to include the design file into sim.bat???Can you please explain in detail..[/q] What about using a text editor and open sim.bat??? [q] I tried it but couldnot get any idea how to do that..[/q] Add your VHDL files in the same way as the other files are listed. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -- View this message in context: <A HREF="http://www.nabble.com/Regarding-JOP-tf2059840.html#a6022237">http://www.nabble.com/Regarding-JOP-tf2059840.html#a6022237</A> Sent from the OpenCores - IP Cores forum at Nabble.com. Hi martin, I got it... I just right clicked the sim.bat and went to edit and modified it accordingly... thanks so much for your help.. Tan Martin Schoeberl wrote: You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. How to include the design file into sim.bat???Can you please explain in detail.. What about using a text editor and open sim.bat??? I tried it but couldnot get any idea how to do that.. Add your VHDL files in the same way as the other files are listed. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6022237 Sent from the OpenCores - IP Cores forum at Nabble.com.

Regarding JOP by Tan on Aug 29, 2006			Tan Posts: 25 Joined: Sep 25, 2010 Last seen: Sep 27, 2010
Hi Martin, I made further progress today,However I am stuck up at a point in testbench. JOP zip there is a testbench for cyclone board(tb_jop.vhd).I modified the testbench according to my project i.e.removed "flash ram".and also made some modifications in the component jop accordinglyincluded transmission pins of I2s) .I tried to use the same "memory" which you instantiated in the tb_jop.when iincluded the same memory in my testbench,modelsim is not responding and when i disabled those signals modelsim is responding but the data is not passed into wr_data pin(because i disabled memory).Can you please tell me which memory to include.In my project I am using "mem_sc.vhd" and "sc_mem_if.vhd".Among these two blocks which memory should I include in my testbench in order to get output from ser_txd pin,and wr_data pin,so that the data can pass to I2s via wishbone.. Tan Martin Schoeberl wrote: [q] [q]You have to add your design file to the ModelSim project. [q]That means: add it to the sim.bat in the modelsim directory. [/q] How to include the design file into sim.bat???Can you please explain in detail..[/q] What about using a text editor and open sim.bat??? [q] I tried it but couldnot get any idea how to do that..[/q] Add your VHDL files in the same way as the other files are listed. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -- View this message in context: <A HREF="http://www.nabble.com/Regarding-JOP-tf2059840.html#a6041107">http://www.nabble.com/Regarding-JOP-tf2059840.html#a6041107</A> Sent from the OpenCores - IP Cores forum at Nabble.com. Hi Martin, I made further progress today,However I am stuck up at a point in testbench. JOP zip there is a testbench for cyclone board(tb_jop.vhd).I modified the testbench according to my project i.e.removed "flash ram".and also made some modifications in the component jop accordinglyincluded transmission pins of I2s) .I tried to use the same "memory" which you instantiated in the tb_jop.when iincluded the same memory in my testbench,modelsim is not responding and when i disabled those signals modelsim is responding but the data is not passed into wr_data pin(because i disabled memory).Can you please tell me which memory to include.In my project I am using "mem_sc.vhd" and "sc_mem_if.vhd".Among these two blocks which memory should I include in my testbench in order to get output from ser_txd pin,and wr_data pin,so that the data can pass to I2s via wishbone.. Tan Martin Schoeberl wrote: You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. How to include the design file into sim.bat???Can you please explain in detail.. What about using a text editor and open sim.bat??? I tried it but couldnot get any idea how to do that.. Add your VHDL files in the same way as the other files are listed. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6041107 Sent from the OpenCores - IP Cores forum at Nabble.com.

Regarding JOP by Unknown on Aug 30, 2006			Not available!
[q] please tell me which memory to include.In my project I am using "mem_sc.vhd" and "sc_mem_if.vhd".Among these two blocks which memory should I include in my testbench in order to get output from ser_txd pin,and wr_data pin,so that the data can pass to I2s via wishbone..[/q] Have you written your Java application that writes some data to your I2S interface? Martin please tell me which memory to include.In my project I am using "mem_sc.vhd" and "sc_mem_if.vhd".Among these two blocks which memory should I include in my testbench in order to get output from ser_txd pin,and wr_data pin,so that the data can pass to I2s via wishbone.. Have you written your Java application that writes some data to your I2S interface? Martin

Regarding JOP by Tan on Oct 23, 2006			Tan Posts: 25 Joined: Sep 25, 2010 Last seen: Sep 27, 2010
Hi Martin, Thank you so much for your help. I would not have completed my project if youwould not have helped me and cleared my doubts. You rescued me like god. thanks so much. i have added your name in my acknowledgement list of my project report. Martin Schoeberl wrote: [q] [q]You have to add your design file to the ModelSim project. [q]That means: add it to the sim.bat in the modelsim directory. [/q] How to include the design file into sim.bat???Can you please explain in detail..[/q] What about using a text editor and open sim.bat??? [q] I tried it but couldnot get any idea how to do that..[/q] Add your VHDL files in the same way as the other files are listed. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -- View this message in context: <A HREF="http://www.nabble.com/Regarding-JOP-tf2059840.html#a6949881">http://www.nabble.com/Regarding-JOP-tf2059840.html#a6949881</A> Sent from the OpenCores - IP Cores mailing list archive at Nabble.com. Hi Martin, Thank you so much for your help. I would not have completed my project if youwould not have helped me and cleared my doubts. You rescued me like god. thanks so much. i have added your name in my acknowledgement list of my project report. Martin Schoeberl wrote: You have to add your design file to the ModelSim project. That means: add it to the sim.bat in the modelsim directory. How to include the design file into sim.bat???Can you please explain in detail.. What about using a text editor and open sim.bat??? I tried it but couldnot get any idea how to do that.. Add your VHDL files in the same way as the other files are listed. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a6949881 Sent from the OpenCores - IP Cores mailing list archive at Nabble.com.

Regarding JOP by Unknown on Oct 23, 2006			Not available!
[q] Hi Martin, Thank you so much for your help. I would not have completed my project if youwould not have helped me and cleared my doubts. You rescued me like god. thanks so much. i have added your name in my acknowledgement list of my project report.[/q] Ok, thanks. Do you have a link to your project report, so we can read about your results? Martin Hi Martin, Thank you so much for your help. I would not have completed my project if youwould not have helped me and cleared my doubts. You rescued me like god. thanks so much. i have added your name in my acknowledgement list of my project report. Ok, thanks. Do you have a link to your project report, so we can read about your results? Martin

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