Hello Friends, I am using JOP in my project.The new version using simpcon.I am interfacing JOP with Wishbone..But when i checked the whole RTL view of JOP,the data is coming out via "sc_mem" block.But tha data from that Block is parallel data(txd pin).To interface it with wishbone i need parallel data.I came to a conclusion that simpcon in JOP is nothing but uart,cnt block.so now I started to check from where there is a chnace of parallel data inorder to absorb that data and connect it to wishbone. so please give me some clue or idea how to proceed further. waiting for reply Cheers Tan -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5674759 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hi Tan,

JOP uses now SimpCon for the memory interface and all IO devices.
In an older version I used Wishbone, but the standard Wishbone memory
interface resulted in one more clock cycle latency. I could only
avoid it with a non-standard early ack signal.

So as fact - use SimpCon for JOP, it's a really simple interface.



What do you want to interface with Wishbone? Memory or IO?

If you have a Wishbone IO interface you can also use the sc2wb.vhd als
SimpCon/Wishbone bridge. I'm using it to interface the AC97 controller
(see scio_dspio.vhd for the usage).



hope this helped,
Martin

Hello Martin, Thank you for your response. My doubt is whether sc2wb contains wishbone in it or should we use seperate interface code for wishbone? Because sc2wb contains all the signals that wishbone have.so i thought to just interface jop with sc2wb and that to a slave device(or another ip core). can you please clear my doubt. Thanks tan -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5679537 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hello Tan,



Yes, that's the way to go.



I don't really see your question in the response. For me you
gave the answer to the first question yourself, didn't you?

Martin

Thanks so much for your reply. We were doubtfull on this issue,so thought of cleraing it.. thanks a ton cheers Tan -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5682154 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hello Martin, I deleted all the memory mappping signals from the code "Extension".(Because I am IO mapping the JOp to SC2WB.) I saw the RTL view of the changed code and noticed that only three blocks are connected (CORE,EXTENSION and SCIO),so now the output from the SCIO block is through UART which is serial data(ser_rxd),but to interface that with SC2WB I need parallel data as SC2WB is having a pin "wd_in"(31 downto 0). But when I try to connect SC2WB to SIPO(code which I wrote) its shows error,saying that it is incompatible.. And what should I do with the address pin?Where should I connect the pin to? There are many pins which remain unconnected..Should I leave them as they are or are they internally connected automatically when two blocks(JOP and sc2wb )are connected.And where are the io_t,io_b,io_l,io_r connected to? Thanks a lot for all your help. -- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5737379 Sent from the OpenCores - IP Cores forum at Nabble.com.

Hi Tan,



Why??? If you want to run Java programs on JOP you need some
external memory. Without memory you can only program in
microcode, which is a pain.



You have to connect the Wishbone device inside scio_xxx.vhd.
See my last post on the example of the dspio configuration.



see above



The io_* pins can be left unconnected, they are for the Cycore
board, or you can cange the scio_xxx.vhd (which is recommended)
to remove them.

Martin

Thanks Martin for all your patient replies..
Sorry in case I am being a pain but am back with a fresh set of questions
today..
Everyday I play with JOP code in order to get the result I want..Today,I
downloaded JOP onto the xilinx kit again(fresh code) and started analysing
the code.Before "SCIO BLOCK" there is an extension block where the output is
"mem_data" and this data is parallel. So to get the output from SCIO block
should I replace SCIO (sc_uart,sc_cnt) with SC2WB.vhd code?I tried this but
am stuck when it comes to mapping memory as the last two block's memories
are connected.

Am trying to confirm if what I am doing is right. Could you please advise me
on how to get the parallel output from SCIO in order to connect it to SC2WB?
The whole idea is to obtain the parallel output from JOP.
Hence connect the output to I2S.






Tan wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5746057 Sent from the OpenCores - IP Cores forum at Nabble.com.

me

No, that's wrong.



Please, please, please: Look into scio_dspio.vhd for an example
how to connect a Wishbone slave to JOP.

Martin

Hi martin,
As you said to take the dspio code as the refernce code,I went through the
code and understood how to interface.However i want to clear what I am doing
is right or not.So here it goes like this...
I took "dspio.vhd" as reference code and wrote the I2s code instead of ac97
and changed the code accordingly...
i hope this time I am doing it correct.

Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5796115 Sent from the OpenCores - IP Cores forum at Nabble.com.

that exactly was the idea ;-)

Martin

Hi,
I have a question.What is the use of simpcon in interconnection of JOP and
wishbone?.
what is the main use of simpcon and the role played by it in the interfacing
process?
cant we interface wishbone directly to JOP?if not why?why are we using
simpcon bridge in between?




Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5896900 Sent from the OpenCores - IP Cores forum at Nabble.com.

SimpCon is JOPs main interconnect to memory and IO.



SimpCon is way more efficient than Wishbone. That's the reason for
SimpCon. You can change JOP to directly use Wishbone or simpler
use the SimpCon/Wishbone bridge. There is no performance gain
when using Wishbone directly. Using the bridge version keeps you
compatible to future updates/enhancements of the memory subsystem
in JOP.

Cheers,
Martin

Hi martin
Thank you so much for your patient replies.
I completed my project which is interfacing JOP and I2S with wishbone.
I just took scio_dspio and replaced tx_i2s_topm signals and inputs,outputs
in the place of ac297 signals and input outputs.
I hope this will make the complete JOP+WISHBONE+I2S.
But during simulation and synthesis it is showing fatal error.If you want i
will send the code.
Please let me know what i did is right or not.
waiting for your answer.
cheers


Martin Schoeberl wrote:
-- View this message in context: http://www.nabble.com/Regarding-JOP-tf2059840.html#a5927148 Sent from the OpenCores - IP Cores forum at Nabble.com.

You could post the relevant lines of the error output.
Perhaps I can find the issue.



Martin