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UART SPORT
by i on Jun 16, 2010 |
i
Posts: 2 Joined: Jun 15, 2010 Last seen: Jun 17, 2010 |
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Hi everyone,
I need to make RX and TX with clock generator for UART SPORT (serial port), and it has to be in Verilog. Maybe someone has a written code, or some parts of it? Thanks |
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RE: UART SPORT
by uCHarry on Jun 17, 2010 |
uCHarry
Posts: 6 Joined: Apr 25, 2010 Last seen: Mar 30, 2018 |
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Hello,
unfortunately I'm writing in VHDL only. But on the Projects site you can find a lot of UART and USART and I'm sure you will find what you need. |
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RE: UART SPORT
by pruby on Jun 29, 2010 |
pruby
Posts: 1 Joined: May 26, 2010 Last seen: Mar 26, 2017 |
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If you're still looking, I just published a Verilog UART project here ( http://opencores.org/project,osdvu ). Would be keen to have someone else do a test drive and provide feedback.
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