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Wishbone based SoC
by Scav on Aug 30, 2010 |
Scav
Posts: 2 Joined: Jun 8, 2010 Last seen: Nov 7, 2010 |
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Hi,
I'm currently working on wishbone bus generation and I need a sample SoC to compare bus architectures. Are there any complete SoCs available which I could use? Ideas for non-existent SoCs are welcome, too. Thanks! |
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RE: Wishbone based SoC
by Rutali on Aug 31, 2010 |
Rutali
Posts: 1 Joined: Jul 24, 2009 Last seen: Jul 28, 2016 |
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Here is an example of Wishbone Bus Functional Model(BFM)
http://opencores.org/project,wishbone_bfm Hope this helps |
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RE: Wishbone based SoC
by rfajardo on Sep 1, 2010 |
rfajardo
Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020 |
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Hi Scav,
minsoc is an OpenRISC SoC completely based on a Wishbone Interconnect. http://opencores.org/project,minsoc HTH, Raul |
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RE: Wishbone based SoC
by Scav on Sep 2, 2010 |
Scav
Posts: 2 Joined: Jun 8, 2010 Last seen: Nov 7, 2010 |
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Thanks,
BFM is good for verification and simple tests. But for performance analysis it would be nice to have realistic traffic. Any ideas? Minsoc is in verilog, which my generator can't parse. :( |
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