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USB 1.1 Device Testbench
by jasonkoberg on Oct 25, 2010
jasonkoberg
Posts: 3
Joined: Apr 28, 2010
Last seen: Jan 6, 2018
I tried to post this, not sure what happened the first time:

Anyway, I am a graduate student at UC San Diego and I am trying to get the device testbench (i.e. testHarness.v in /usbDevice) working. The specifications said I should be able to request IN transactions from endpoint 1 but I am having no luck. I believe I need to configure the device but I cannot find the correct registers to write to to achieve this. I am currently using the 'wb_master_model' module in the test harness and calling its tasks for reading/writing registers in the master. Does anyone know which registers to write to achieve to make it so I can process IN transactions from endpoint 1 (A basic mouse)? Or does someone have a modified testbench that does this successfully?

Any insight is helpful.

Thanks!
Jason
RE: USB 1.1 Device Testbench
by jasonkoberg on Oct 26, 2010
jasonkoberg
Posts: 3
Joined: Apr 28, 2010
Last seen: Jan 6, 2018
Right now, as a start, I am trying to perform a GET_STATUS from endpoint0 on the device. The USB specification seems to require that I perform a SETUP transaction followed by 8 DATA0 transactions. I can successfully have the usbHost put a SETUP transaction out but I receive no response from the endpoint.

Thanks,
Jason
RE: USB 1.1 Device Testbench
by M_artin on Mar 5, 2011
M_artin
Posts: 4
Joined: Apr 6, 2010
Last seen: Jan 4, 2017
Hi,
I just struggle to upload my USB FS test bench - not succeded jet. But some lines from my test case may help:


setup(usb, X"00", X"0"); --Send Setup to addr 0, endp 0 ..
send_D0(usb,(X"80",X"06",X"00",X"01",X"00",X"00",X"40",X"00"));
-- .. 'Get Device descriptor'
wait_slv(usb); --Recv ACK
in_token(usb, X"00", X"0"); --Send IN-Token
wait_slv(usb); --Recv Data1 Device Discriptor
send_ack(usb); --Send ACK
setup(usb, X"00", X"0"); --Setup to addr 0, endp 0 ..
send_D0(usb,(X"00",X"05",X"03",X"00",X"00",X"00",X"00",X"00"));
-- .. 'Set Address'
wait_slv(usb); --Recv ACK
in_token(usb, X"00", X"0"); --Send IN-Token
wait_slv(usb); --Recv Data0 zero Length
send_ack(usb); --Send ACK

--Now we may use the new address :
out_token(usb, X"03", X"1"); --Send Out-Token to Endpoint 1
send_D0(usb, (X"11",X"22",X"33",X"44",X"55",X"66",X"77",X"88"));
wait_slv(usb);


What is important is the 'dummy' IN-Token to the old device address and endpoint 0 !!!
You will receive a zero-length data packet

God luck
M_artin
RE: USB 1.1 Device Testbench
by jinger on Jun 16, 2011
jinger
Posts: 2
Joined: Oct 9, 2008
Last seen: Oct 4, 2013
hello,M_artin
I am glad to see your help here because I am looking for the testbench. Have you uploaded the TB somewhere�if not yet, can you provide some more detail info for the testbench. I think it will be great helpful for reference !
thanks!
Y.J
RE: USB 1.1 Device Testbench
by M_artin on Jun 16, 2011
M_artin
Posts: 4
Joined: Apr 6, 2010
Last seen: Jan 4, 2017
Hello jinger,
you will find the Testbench in OpenCores -> Projects -> Communication controller -> USB 1.1 Simulation (VHDL).
Download the tar file, expand it and look into the trunk directory.
You may look also into
http://opencores.org/project,usb11_sim_model,downloads
for the documentation in PDF format.
Have fun
Martin
RE: USB 1.1 Device Testbench
by jinger on Jun 23, 2011
jinger
Posts: 2
Joined: Oct 9, 2008
Last seen: Oct 4, 2013
hello,M_artin
Thank you for your reply. I have downloaded the project testbench you metioned. I found in the PDF SPEC the translated VHDL
USB FS PHY and USB serial files should be included. However, I cannt find that in the HDL files directory. And more, I have downloaded the usb phy designed by Rudolf
in opencores.org, and have not found the usb serial designed by Joris. Could you give me some instructions? Thanks much!
regards.
jinger.
RE: USB 1.1 Device Testbench
by M_artin on Jun 25, 2011
M_artin
Posts: 4
Joined: Apr 6, 2010
Last seen: Jan 4, 2017
The USB serial design from Joris Rantwijk mentiond in the docu can be found at http://jorisvr.nl/usb/
M_artin
RE: USB 1.1 Device Testbench
by flirchuck on Jun 25, 2011
flirchuck
Posts: 1
Joined: Jul 2, 2008
Last seen: May 21, 2020
The USB Serial from Joris is also used in this OpenCores project:

http://opencores.org/project,opb_usblite

Chuck
RE: USB 1.1 Device Testbench
by SadikO on Apr 3, 2013
SadikO
Posts: 3
Joined: Jan 7, 2013
Last seen: Jun 18, 2014
When I try to run the usb simulation (vhdl) ( http://opencores.org/project,usb11_sim_model )
in modelsiom, I always get the error message:

pid: 00000110
# ** Error: PID error
# Time: 6234 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# pid: 00000000
# ** Error: PID error
# Time: 6906 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# ** Error: PID is zero
# Time: 6906 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# pid: 00000001
# ** Error: PID error
# Time: 7578 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# pid: 01000000
# ** Error: PID error
# Time: 9594 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# ** Error: PID is zero
# Time: 9594 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# pid: 00000000
# ** Error: PID error
# Time: 10266 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# ** Error: PID is zero
# Time: 10266 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor
# pid: 11011101
# ** Error: PID error
# Time: 10938 ns Iteration: 1 Instance: /usb_tb/usb_fs_master/usb_fs_monitor


as you can see Ive added a debug print to see what the pid is. unfortunately I have no clue what I am doing wrong. Can you help me?
I want to simulate Martin Neumann's "USB 1.1 PHY (VHDL)" (http://opencores.org/project,usb11_phy_translation )
RE: USB 1.1 Device Testbench
by SadikO on Apr 4, 2013
SadikO
Posts: 3
Joined: Jan 7, 2013
Last seen: Jun 18, 2014
sorry, I forgot to use the slave, that's why I got pid error.

RE: USB 1.1 Device Testbench
by Goyban on May 29, 2015
Goyban
Posts: 1
Joined: Dec 20, 2013
Last seen: Jun 29, 2015
hi guys i'm a little new to vhdl
i downloaded the USB 1.1 Simulation (VHDL) but it wont work
how can i test it ?
anyone did it ? i really need it ....
i can't right the test bench file it's confusing for me
if some one has the working testbench file i appreciate that ...
thank you
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