i8080 compatible processor using Am29XX bit slice family and microcoded design :: Overview

Project maintainers


Name: am9080_cpu_based_on_microcoded_am29xx_bit-slices
Created: Jan 4, 2018
Updated: Jan 11, 2018
SVN Updated: Jan 15, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 2 solved

★ Star 2 you like it: star it!

Other project properties

Category: Processor
Language: VHDL
Development status: Beta
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL



Implement i8080 compatible processor code in VHDL, using bit-slice technology and microcoding.


Retro-computing is fun and rich in learning. One fascinating aspect is bit-slice technology popular in 1970-ies, which was naturally combined with microcoded processor architectures. In some ways, it was another take on the idea of "programmable" logic, within the limits of the day. Researching the era, I stumbled upon following article:

AMD engineers describe building an "Am9080" CPU (i8080 second-sourced) using popular Amd29XX bit-slice product. The description was very detailed, including circuit schemas and microcode, and it seemed like a fun project to "reverse-engineer" (given that the article was written 30+ years ago, hoping not to run into any copyright issues...) and re-implement in VHDL.


Very simple hardware debugging was used - a single step circuit combined with key signals from the guts of the processor (such as microinstruction address and data word, macro instruction register, register contents etc.) being exposed through 16-bit "debug" bus to LED display. Simple "test" assembler programs executed allowed instruction execution to be observed clock by clock cycle and fixed. The original microcode listing contained a few bugs that prevented for example RST n to function well when presented at INTA cycle.


Instead of boring test bench, I decided to write an equivalent of once popular "evaluation system" boards, containing:

-2 kB ROM
-256 bytes RAM
-parallel I/O port
-interrupt controller
-varible clock circuitry (from 1Hz to 25MHz)

Such system boards came with basic bootstrap loaders and monitors. The fact that the system can run and execute (most) commands of Altair monitor is encouraging, and sufficient to merit "beta" status. This is how it looks in "action":

Hardware used:

* Micronova Mercury FPGA development board
* Mercury baseboard
* Parallax USB2SER development board

Development tools:

* Xilinx ISE 14.7 (nt) - free version

* Zmac 8080/Z80 assembler for PC
Used to assemble the boot.asm and slighly changed AltMon.asm into *.hex files which are then loaded to 2 ROMs during VHDL compile

* Parallax Propeller IDE serial terminal
Probably most other generic serial terminal window programs can be used

Software and code (re)used:

* Altair monitor program by Mike Douglas
Minimal changes to assemble to address 0x0400 etc.

* VHDL uart-for-fpga by Jakub Cabal (
The "ACIA" component wraps it to expose to CPU a "device" somewhat similar to classic MC6850 ACIA

* VHDL Am2901 by Amr Nasr (
In current iteration this is replaced by my own simpler VHDL Am2901c, but this was the inspiration

* VHDL Am2909 by Stanislaw Deniziak (

Possible next steps:

- run 8080 instruction verification program
- use audio in/out ports on baseboard for casette tape "mass storage" :-)
- port to other FPGA boards with more resources, possibly creating a CP/M microcomputer
- implement 8085 instruction set
- use in other projects

Known problems:

- interrupt ack only works for RST n instructions, not CALL. However, few if any 8080 systems used the latter
- the processor implementation is clunky - clean "RTL" state machine would be much more optimized and smaller / faster than many components and subcomponents I had to write to replicate 74XX-type logic as individual "ICs". However it is fun to see "guts" of processors as they used to be in that era.

It would be exciting to see if somebody could use this core in their own projects. If so, shoot me an email to

Latest version of the source code (under appropriate license) is available at

© copyright 1999-2018, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.