OpenCores

Project Oberon with SDRAM

Project maintainers

Details

Name: oberon_sdram
Created: Feb 10, 2017
Updated: Feb 12, 2017
SVN Updated: Feb 12, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:System on Chip
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

Project Oberon http://www.projectoberon.com modified to use SDRAM instead of static RAM
Static RAM is old technology in FPGA world, and 1MB 32bit SRAM is hard to find on FPGA dev boards.
I upgraded this great project with a cache memory, which is able to interface SDRAM and DDRAM.
I uploaded the project archives for FleaFpga and for PapilioPro.
I will also provide DE2-115 and Nexys4 versions.