Priority Encoder :: Overview

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Name: priority_encoder
Created: Aug 23, 2015
Updated: Oct 5, 2015
SVN Updated: Sep 10, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Alpha
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


Module of parameterized encoder based on verilog. Synthesized to multi-input OR elements.

Example of 16 to 4 priority encode:

parameter IN_LINES=16;
parameter OUT_LINES=$clog2(IN_LINES); //4

wire [(IN_LINES-1):0] in_data;
wire [(OUT_LINES-1):0] out_data;

prio_encoder #(.LINES(IN_LINES)) pe0(.in(in_data), .out(out_data));

The module is based on the this scheme

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