Module of parameterized encoder based on verilog. Synthesized to multi-input OR elements.
Example of 16 to 4 priority encode:
parameter IN_LINES=16;
parameter OUT_LINES=$clog2(IN_LINES); //4
wire [(IN_LINES-1):0] in_data;
wire [(OUT_LINES-1):0] out_data;
prio_encoder #(.LINES(IN_LINES)) pe0(.in(in_data), .out(out_data));
The module is based on the this scheme