SATA PHY :: Overview

Project maintainers


Name: sata_phy
Created: Jul 12, 2012
Updated: Mar 10, 2014
SVN Updated: Jul 12, 2012
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


SATA PHY layer which can be implemented as either a host or device for Xilinx 6 series devices.

A host controller core with AXI interface is available, contact me for more information.

© copyright 1999-2017, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.