SATA PHY
Project maintainers
Details
Name: sata_phy
Created: Jul 12, 2012
Updated: Mar 10, 2014
SVN Updated: Jul 12, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: Jul 12, 2012
Updated: Mar 10, 2014
SVN Updated: Jul 12, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star4you like it: star it!
Other project properties
Category:Communication controller
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
SATA PHY layer which can be implemented as either a host or device for Xilinx 6 series devices.
A host controller core with AXI interface is available, contact me for more information.
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