openVeriFLA - FPGA logic analyzer

openVeriFLA 2022 - FPGA logic analyzer

openVeriFLA 2022 is an FPGA logic analyzer. The host computer software
is written in Java (from 1.0) and Python (from 3.0), in both being fully supported.
The HDL code is written in Verilog and VHDL, in both languages being fully supported.
This project helps in on-board testing and debugging of the FPGA projects.
This is done by real-time capturing and then graphically displaying
the signals transitions that happen inside the FPGA chip.
Having a didactic scope, openVeriFLA is designed & tested on and for small projects.
openVeriFLA comes with its reference manual.

openVeriFLA 3.0 is on https://github.com/laurentiuduca/openverifla

openVeriFLA 2.4 is on opencores.org

I hope you will find it usefull :)
Do not use 1.0.3 and older versions because are obsolete.
Please provide feedback!

Features

on-the-fly capture, graphical display

Status

ready to use