openVeriFLA - FPGA logic analyzer :: Overview

Project maintainers


Name: openverifla
Created: Jul 31, 2007
Updated: Aug 9, 2018
SVN Updated: Aug 20, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Library
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

openVeriFLA - FPGA logic analyzer

openVeriFLA is an FPGA logic analyzer written in Verilog and Java.
It helps in on-board testing and debugging of the FPGA projects.
This is done by real-time capturing and then graphically displaying
the signals transitions that happen inside the FPGA chip.
Having a didactic scope, it is designed for small projects.
Please note that learning to use this logic analyzer may require more than an hour,
while understanding the source code may require a few days.

openVeriFLA 2.1 has been released. I hope to find it usefull :)
Do not use 1.0.3 and older versions because are obsolete.


- on-the-fly capture, graphical display


- ready to use

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