Created: Jul 31, 2007
Updated: Oct 16, 2018
SVN Updated: Nov 9, 2018
Latest version: download
(might take a bit to start...)
0 reported / 0 solved
Star0you like it: star it!
Other project properties
openVeriFLA 2018 - FPGA logic analyzer
openVeriFLA is an FPGA logic analyzer. The host computer software is written in Java,
so it is platform independent. The HDL code is written in Verilog and VHDL,
in both languages being fully supported.
This project helps in on-board testing and debugging of the FPGA projects
and also debugging protocols on the wires that connect the FPGA board with other development boards.
This is done by real-time capturing and then graphically displaying
the signals transitions that happen inside the FPGA chip.
Having a didactic scope, openVeriFLA is designed & tested on and for small projects.
openVeriFLA comes with its reference manual.
openVeriFLA 2.3 has been released. I hope to find it usefull :)
Do not use 1.0.3 and older versions because are obsolete.
- on-the-fly capture, graphical display
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.