openVeriFLA 2019 is an FPGA logic analyzer. The host computer software is written in Java,
so it is platform independent. The HDL code is written in Verilog and VHDL,
in both languages being fully supported.
This project helps in on-board testing and debugging of the FPGA projects.
This is done by real-time capturing and then graphically displaying
the signals transitions that happen inside the FPGA chip.
Having a didactic scope, openVeriFLA is designed & tested on and for small projects.
openVeriFLA comes with its reference manual.
openVeriFLA 2.4 has been released
and is also available on https://github.com/laurentiuduca/openverifla
I hope you will find it usefull :)
Do not use 1.0.3 and older versions because are obsolete.
Please provide feedback!
on-the-fly capture, graphical display
ready to use