openVeriFLA - FPGA logic analyzer

Project maintainers


Name: openverifla
Created: Jul 31, 2007
Updated: Oct 11, 2022
SVN Updated: Feb 7, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!

Other project properties

Language:Verilog & VHDL
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

openVeriFLA 2022 - FPGA logic analyzer

openVeriFLA 2022 is an FPGA logic analyzer. The host computer software
is written in Java (from 1.0) and Python (from 3.0), in both being fully supported.
The HDL code is written in Verilog and VHDL, in both languages being fully supported.
This project helps in on-board testing and debugging of the FPGA projects.
This is done by real-time capturing and then graphically displaying
the signals transitions that happen inside the FPGA chip.
Having a didactic scope, openVeriFLA is designed & tested on and for small projects.
openVeriFLA comes with its reference manual.

openVeriFLA 3.0 is on

openVeriFLA 2.4 is on

I hope you will find it usefull :)
Do not use 1.0.3 and older versions because are obsolete.
Please provide feedback!


on-the-fly capture, graphical display


ready to use