Generic AXI to AHB bridge :: Overview

Project maintainers


Name: robust_axi2ahb
Created: Apr 13, 2011
Updated: Dec 29, 2017
SVN Updated: Jul 3, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved

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Other project properties

Category: System on Chip
Language: Verilog
Development status: Alpha
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB slave error. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from

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