OpenCores

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Details

Name: 4_fir_filter
Created: Jan 2, 2021
Updated: Jan 2, 2021
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties

Category:DSP core
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

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The url of the svn repository is: https://opencores.org/websvn/listing/4_fir_filter/4_fir_filter