OpenCores

6809 and 6309 Compatible core :: Overview

Project maintainers

Details

Name: 6809_6309_compatible_core
Created: Dec 23, 2013
Updated: Aug 9, 2019
SVN Updated: Jan 25, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 5 reported / 3 solved
Star2you like it: star it!

Other project properties

Category:Processor
Language:Verilog
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

A verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core.

Goals:

- Execute all implemented opcodes
- Allow asnychronous memories
- >40 MHz clock

Status

- Most instructions need less clocks than the original.
- Synthesizes in Lattice Diamond for the MachXO2 requiring ~1260 Slices (two-cycle multiplier) @ >40 MHz, tested, works.
- Synthesizes in XST for Spartan 2 using a bit less than 1200 Slices (fits in a XC2S100). Testing pending.
- Synthesizes in XST for Spartan 3 using ~1150 Slices, hw-multiplier. Testing on real FPGA pending.
- A simple vga text controller has been added, it needs some 70 SLICES and two blocks of ram of 4 kbyte each
for font and text. It only outputs b/w. It may be removed to make the code smaller.

- All 6809 opcodes have been implemented.

- 6309 opcodes have to be added