A verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core.
- Execute all implemented opcodes
- Allow asnychronous memories
- >40 MHz clock
- Most instructions need less clocks than the original.
- Synthesizes in Lattice Diamond for the MachXO2 requiring ~1260 Slices (two-cycle multiplier) @ >40 MHz, tested, works.
- Synthesizes in XST for Spartan 2 using a bit less than 1200 Slices (fits in a XC2S100). Testing pending.
- Synthesizes in XST for Spartan 3 using ~1150 Slices, hw-multiplier. Testing on real FPGA pending.
- A simple vga text controller has been added, it needs some 70 SLICES and two blocks of ram of 4 kbyte each
for font and text. It only outputs b/w. It may be removed to make the code smaller.
- All 6809 opcodes have been implemented.
- 6309 opcodes have to be added