Devic, Goran

A-Z80 CPU

Hi Goran,
Firstly, congratulations for the superb job you’ve done in creating this model and thanks for all your hard work.

I’ve been using the A-Z80 core in a Xilinx FPGA to replace a Z80 in a Cambridge Z88 and unfortunately it didn’t work initially. I eventually tracked the problem down to the timing of the I/O read instructions (in a,(c) in this case). The read latch enable signal (SYNTHESIZED_WIRE_2 in data_pins.v) becomes active during the TW cycle of the I/O read instructions, thus latching the data in the middle of the instruction rather than at the end as the real Z80 does. This is a problem for the Z88 hardware since the read data is not stable at this time.

I have verified that this is the cause of my problem by delaying the read enable signal (bus_db_pin_re in z80_top_direct_n.v) by 1 clock cycle when nIORQ is low so that it is active during the T3 clock cycle. With this modification the core works perfectly with the Z88 hardware even putting the contents of the I register onto the address bus during halt, which other models I tried did not. This feature is used by the Z88 to detect key presses while “asleep”.
Martin

I/O read timing

Overall I am impressed with the A-Z80 core but it seems that the Processor does not drive IORQn low during the IAck Cycle. 

I am running the A-Z80 on a Xilinx UltraScale+ in the Xilinx Vivado 18.2 tool ... so far, I am working only with simulations ...I have found that the A-Z80 does not respond as expected during the Interrupt Request / Interrupt Acknowledge Cycle as specified in the Z80 CPU User Manual (UM008011-0816 Page 13 Figure 9).

Per the User Manual, IORQn should be driven low for 1.5 clock cycles starting 2.5 clocks into the cycle.  It does not.

I have tried it using my Z80 Assembly Program and with the Hello_World program provided with the core.  The default interrupt mode in the supplied Hello_Word is IM2 but I tried it with IM0 and IM1 as well by modifying Hello_World and IORQ never responded as expected in the IAck Cycle.  

IORQn does appear to respond appropriately in Port I/O Cycles.

To verify file integrity, I re-downloaded a fresh copy of the core and had the same problem.  

In my program I write to an address that causes external logic to generate an INTn but when simulating Hello_World I forced INTn low ... the processor responded with what appeared to be an Interrupt Acknowledge Cycle except that IORQn did not go low.

IORQn in IAck Cycle

Have been unable to make interrupt acknowledge work.

interrupt mode 2 set.

monitoring IORQ and M1 not happening at the same time.

INT_ACK

INIR instruction acts like INI. But it should repeat IN instruction till B=0.

Browse

A-Z80 CPU