a VHDL 16550 UART core

The comments about the clock configuration are correct. The baud rate generator creates a clock enable which is used by the Transmitter and Receiver modules – they operate at the same rate as B_CLK.

As long as the user wants to use the Baud rate generator to set the baud rate, there is no problem. If some one wants to by-pass the Baud rate generator, it should be easy modify the source code.