A. LeFevre, Howard

a VHDL 16550 UART core

Vivado 2016.4
FPGA: XCKU115

When trying to empty the RX Fifo, with CS and WR in single shot mode (only '1' for one clock cycle) and continiously reading the RX Fifo, the same read is outputted.

When doing a TX Fifo write followed by a RX Fifo read, the RX fifo counter is incremented. 

Example:

RX Fifo Read 20 times outputs last known TX Fifo (lets say 0x30) each read.

----------------------------

Tx Fifo Write 0x00
RX Fifo read, 0x30
TX Fifo Write 0x00
RX Fifo read, 0x31
...
...
...
Tx fifo write 0x00
Rx fifo read 0x00
..
..
Tx fifo write 0x01
Rx fifo read 0x01
Tx fifo write 0x02
Rx fifo read 0x02
..
..
Tx fifo write 0x20
Rx fifo read 0x20

--------------------------------

It seems that the TX and RX Fifo counters are correlated when they should be independent of each other. Is there something I am doing that is just incorrect or am I misnunderstanding something?

RX Fifo Counter

A bunch of source files are missing.

1. gh_edge_det.vhd
2. gh_register_ce.vhd
3. gh_DECODE_3to8.vhd
4. gh_jkff.vhd
5. gh_baud_rate_gen.vhd
6. gh_counter_down_ce_ld_tc.vhd
7. gh_edge_det_XCD.vhd

Missing Source Files

The VHDL 16550 UART generates an error using Xilinx iSim (I’m using 12.3 M.70d). Ther error is: 
ERROR: Value -2147483648 is out of valid range : 0 TO 8 

This is caused by line 29 of gh_uart_Rx_8bit.vhd, which reads: 
num_bits : in integer; 
I think that this should read 
num_bits : in integer:=8;

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a VHDL 16550 UART core