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a VHDL 16550 UART core
Overview
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Bugtracker
Open
3
Closed
11
All
14
New issue
RX Fifo Counter
Bug
#14 opened almost 2 years by NULL
Missing Source Files
#12 opened over 4 years by D3monhun73r
Xilinx iSim generates "out of valid range" error
Bug
#11 opened over 13 years by c.noble
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