a VHDL 16550 UART core

Vivado 2016.4 FPGA: XCKU115

When trying to empty the RX Fifo, with CS and WR in single shot mode (only '1' for one clock cycle) and continiously reading the RX Fifo, the same read is outputted.

When doing a TX Fifo write followed by a RX Fifo read, the RX fifo counter is incremented.

Example:

RX Fifo Read 20 times outputs last known TX Fifo (lets say 0x30) each read.

Tx Fifo Write 0x00 RX Fifo read, 0x30 TX Fifo Write 0x00 RX Fifo read, 0x31 ... ... ... Tx fifo write 0x00 Rx fifo read 0x00 .. .. Tx fifo write 0x01 Rx fifo read 0x01 Tx fifo write 0x02 Rx fifo read 0x02 .. .. Tx fifo write 0x20 Rx fifo read 0x20

It seems that the TX and RX Fifo counters are correlated when they should be independent of each other. Is there something I am doing that is just incorrect or am I misnunderstanding something?