a VHDL 16550 UART core
Project maintainers
Details
Created: Feb 17, 2006
Updated: Dec 8, 2010
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 14 reported / 11 solved
Other project properties
Language:VHDL
Development status:Stable
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License:
Description
A UART that is compatible with the industry standard 16550D
Includes wrappers for the Wishbone and AMBA APB busses
Features
Uses parts from the project (3.17 or later)
Sticky parity is not supported
FIFO's are always enabled
Status
Design is finished
18 Jun 2007
P. Azkarate's addition of range for integers in Rx, Tx modules
this helps when using the Altera tools
12 July 2007
fix a couple problems found by Matthias Klemm with 5, 6, and 7 bit transfers
14 July 2007
Correct FCR bit 3 information (DMA Mode control)
4 Aug 2007
fix some TOI problems
18 Aug 2007
add stopB to sensitivity list in TX module (works the same, but removes warning)
12 Oct 2007
fixed the bug reports (dated 10/11 Oct 2007)
THRE Interrupt will now be generated when trans FIFO is empty and interrupt enable bit changes from disabled to enabled. (note on THRE operation added par 3.3)
The Receiver Line Status Interrupt is cleared as suggested by Matthias Klemm (note to bug report dated 10/12/07) (mod to this fix 13 oct 2007)
21 July 2008
mod equ for iBreak_ITR, as suggested by Nathan Z.