a VHDL 16550 UART core

A bunch of source files are missing.

1. gh_edge_det.vhd
2. gh_register_ce.vhd
3. gh_DECODE_3to8.vhd
4. gh_jkff.vhd
5. gh_baud_rate_gen.vhd
6. gh_counter_down_ce_ld_tc.vhd
7. gh_edge_det_XCD.vhd

https://github.com/freecores/uart_fpga_slow_control/tree/master/code/library