a VHDL 16550 UART core

Hi Howard,

I'm using your UART core with the associated gh library and I have some trouble. When the dividing register (DLM,DLL) is set to 1, to have the maximum baud rate, the UART simply don't work. After analyzing the design, I've located the problem in the gh_baud_rate_gen entity.

In this entity, when "rate" value is set to 1, the counter U3 is stopped and "count" output stay to value 1. Then the entity output "rCE" is fixed to '1'. Finally signal "BRC16x" in gh_uart_16550 entity is always '1'. I've tried to use the "BR_CLK" input signal to directly drive the "rCE" output. But UART doesn't work. It works when using "not BR_CLK" but I can't explain why and it could be dangerous for synchronization.

Could you please explain me how the BRC16x is used in the UART entity. Do you have some idea to find out the problem or to solve it ?

info: gh_baud_rate_gen version 2.1 gh_uart_16550 version 2.8

Thank you for your help.

Best regards,

Cyril BEGUET

As stated in the documentation, the baud rate generator will divide the BR_clk by any value between 2 and 2^16-1. Entering a 1 into the baud rate register would imply the the clock is divided by one (which is not allowed).

The BRC16x is used as a clock enable - BR_clk is the clock - in the TX and RX modules.

It works as it was designed to work.

If you tie BRC16x to a logic one, it might do what you want it to, I have not tested this, I am not sure this will work!