a VHDL 16550 UART core
No "Emptx Transmit Holding" Bit is set #13
Closed srmeister opened this issue over 3 years ago
srmeister commented over 3 years ago
The bit for "Empty Transmitter Holding Register", is not set. It is bit 6 of LSR.
So the Software does not see if the FIFO is full, if it is polling this bit. It keeps on writing into the FIFO after the 16 bytes are full and out comes garbage.
srmeister commented over 3 years ago
sorry i was just too stupid about reading the LSR byte correctly... there is actually no bug
srmeister closed this over 3 years ago
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