a VHDL 16550 UART core

Timeout interrupts are now disabled with the receive interrupts enabled/disabled together.

I have run into this 'bug' myself just today while playing with the core. I think I got it fixed with the following change :

on file gh_uart_16550.vhd

CHANGE : -- Modificat del original*** DJJ 2-8-2007 -- IRQ <= '1' when ((ITR3 or ITR2 or TOI or ITR1 or ITR0) = '1') else -- '0';

with IRQ <= '1' when ((TOI = '1' and IER(0) = '1') or (ITR3 or ITR2 or ITR1 or ITR0) = '1') else '0';

disclaimer : my knowledge of the core is rather limited !!!