a VHDL 16550 UART core

It is my understanding that an interrupt should be generated as soon as the Transmitter Holding Register Empty Interrupt is enabled (bit 1 IER). My simulation shows this is not the case. Linux driver (8250.c) flags this behaviour with UART_BUG_TXEN, so maybe this is not a bug and this behaviour is intended.

The associated comment in 8250.c is actually:

• Test for UARTs that do not reassert THRE when the
• transmitter is idle and the interrupt has already
• been cleared. Real 16550s should always reassert
• this interrupt whenever the transmitter is idle and
• the interrupt is enabled. Delays are necessary to
• allow register changes to become visible. ...so it's a bug, but it doesn't kill serial port operation at least on Linux. However, it enables a 5Hz timeout timer per UART in Linux, which is a killer for low-power applications with multiple serial ports. 0.2 seconds is also a long time in some timing-critical applications (UPS signals, anyone?). Apparently, there are some compatibility-arguments for doing it either way, though, see http://www.ussg.iu.edu/hypermail/linux/kernel/0603.3/2543.html for example which seems to suggest a third, more complicated way of doing it. A quick web-search indicates something like that has been discussed on Opencores forums several years back as well. Unfortunately I've personally not had time to look into that in detail, so I don't have a solution to offer at this time, but add the above considerations to the issue.