a VHDL 16550 UART core

Problem: Tx FIFO (U28) latch data two times on one ABP write cycle. Two wr pluses are generated on FIFO wr input. Edge detection (U3) in ABP wrapper detect two rising edge instead of one. There is a mistake in CS equation.

Solution: in file gh_uart_16550_amba_apb_wrapper.vhd, line 171, change CS <= '1' when ((PSEL = '1') and (PENABLE = '0')) else '0'; to CS <= '1' when ((PSEL = '1') and (PENABLE = '1')) else '0';

If the signals have the timing as shown in the AMBA Specification (Rev 2.0) page 5-5 (figure 5-3) wrapper works fine. If PSEL remains high for an extra clock cycle (without the data for a new transfer in progress - which should not happen - read the second paragraph after figure 5-3) an extra write will happen to the core - but, while repeating myself, PSEL being high for an extra clock period violates the specification.