Parameterizable adder tree
Project maintainers
Details
Name: adder_tree
Created: Mar 17, 2018
Updated: Mar 23, 2018
SVN Updated: Mar 27, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Mar 17, 2018
Updated: Mar 23, 2018
SVN Updated: Mar 27, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star5you like it: star it!
Other project properties
Category:Arithmetic core
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Parameterizable Verilog module that calculate sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array systems.
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.