All components are modeled as Altera Qsys components. Altera Qsys connects all parts together, and supplies the SDRAM controller.
The ao486 project is currently only running on the Terasic DE2-115 board.
|Unit||Logic cells||M9K memory blocks|
|onchip for nios2||0||32|
The fitter raport after compiling all components of the ao486 project is as follows:
Fitter Status : Successful - Sun Mar 30 21:00:13 2014
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : soc
Top-level Entity Name : soc
Family : Cyclone IV E
Device : EP4CE115F29C7
Timing Models : Final
Total logic elements : 91,256 / 114,480 ( 80 % )
Total combinational functions : 86,811 / 114,480 ( 76 % )
Dedicated logic registers : 26,746 / 114,480 ( 23 % )
Total registers : 26865
Total pins : 108 / 529 ( 20 % )
Total virtual pins : 0
Total memory bits : 2,993,408 / 3,981,312 ( 75 % )
Embedded Multiplier 9-bit elements : 44 / 532 ( 8 % )
Total PLLs : 1 / 4 ( 25 % )
The maximum frequency is 39 MHz. The project uses a 30 MHz clock.
|Dhryston 1 Benchmark Non-Optimised||1.00 VAX MIPS|
|Dhryston 1 Benchmark Optimised||4.58 VAX MIPS|
|Dhryston 2 Benchmark Non-Optimised||1.01 VAX MIPS|
|Dhryston 2 Benchmark Optimised||3.84 VAX MIPS|
The ao486 project uses the BIOS from the Bochs project (http://bochs.sourceforge.net, version 2.6.2). Some minor changes were required to support the hard drive.
The VGA BIOS is from the VGABIOS project (http://www.nongnu.org/vgabios, version 0.7a). No changes were required. The VGA model does not have VBE extensions, so the extensions were disabled.
The ao486 SoC uses a Altera NIOS2 processor for managing all components and displaying the contents of the On Screen Display.
The OSD allows the user to insert and remove floppy disks.
The binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.
The binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.
The binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios project.