Osman, Aleksander

ao68000 - Wishbone 68000 core

It seems to me there is a problem executing BRA instruction.
For example, if the instruction is 0x60FE, I expect next_pc = current_pc (i.e. next_pc = current_pc + 2 +0xffffffe), instead i see next_pc = current_pc-2.....

BRA problem

PRIOLITY LOW

I tested ao68000 by different simulator.

Veritak
http://www.sugawara-systems.com/

OK.

Modelsim-Altera starter edition
htp://www.altera.com/

There are some problems.
A position defining a signal is bad.
CODE use it before define.
When I changed the place, simulation was possible.

I want you to revise it if there is the time that is enough for you.

---- modelsim message ----

** Error: ao68000.v(1416): Undefined variable: pc_valid.
** Error: ao68000.v(1498): 'pc_valid' already declared in this scope (registers).
** Error: ao68000.v(1703): 'dn_byteena' already declared in this scope (memory_registers).
** Error: ao68000.v(2911): Undefined variable: micro_pc_0.
** Error: ao68000.v(2926): Undefined variable: micro_pc_1.
** Error: ao68000.v(2936): 'micro_pc_0' already declared in this scope (microcode_branch).
** Error: ao68000.v(2937): 'micro_pc_1' already declared in this scope (microcode_branch).

---- modelsim message ----

Thank you.

adapt to modelsim

Is this specifications of ao68000?

The MC68000 uses UDS and LDS as a byte lane in a read-cycle.

ao68000 uses the SEL signal as a byte lane.
During a read-cycle, it is always SEL=4'b1111.
In the read-cycle of 1 byte, SEL=4'b1111.

If this difference is specifications of ao68000, I do not assume it a problem.
However, I think it to be slightly inconvenient.

sel signal

I tested ao68000 in verilog simulator.
I tried 68000 monotr program,but dose not work.

I think DBRA(DBcc) have a problem.

68k montor source :

	lea	traperr(pc),a0
	lea	$80,a1
	moveq	#15,d0
trapset	move.l	a0,(a1)+
	dbra	d0,trapset

simulation d0 value :
$0000000f
$0000000e
.
.
$00000000
$0000ffff <- dbra loop not end !!
$0000fffe <- ????

Thank you

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ao68000 - Wishbone 68000 core