The ASPIDA project has implemented an asynchronous IP of the DLX Instruction Set Architecture (ISA) with incorporated support for ISA conversion so it can be easily converted to any RISC ISA. The DLX architecture, is well-supported by existing software development tools (compiler, assembler, loader, instruction set simulator and debugger).
The synchronous single-pipeline architecture, which is standard for the basic synchronous DLX implementations, is identical to the architecture of the asynchronous version. A suitable Open IP interface (WISHBONE) is embedded onto the processor to enable it to be integrated into any Open IP SOC system. In addition, the ASPIDA project issues a new Open IP interface standard based on asynchronous technology (CHAIN), and support for this new Open IP interface is also embedded onto the processor core.
A design flow that is based as much as possible on existing EDA tools for all design steps, and which is part of the background technology brought in by the partners, has been used in order to produce a portable netlist, and to distribute all the intermediate HDL files used for high-level and gate-level design. The final product is technology-independent and timing-independent and in a form suitable for integration using only standard, industrial tools and flows, with no dependence on asynchronous tools and specific knowledge of asynchronous design for potential end users.
- Technology-portable processor core
- Fully-asynchronous core for low-power, low-EMI
- Industrial-quality testability (internal scan)
- WISHBONE interface
- Core includes additional novel asynchronous bus, CHAIN (CHip Area INterconnect)
- Targetted for ASIC EDA flows
- Project is completed
- Fully Working FPGA Implementation is available on Xilinx Spartan 2E device
- ASIC Implementation completed and tested
- Download FAQ and all the sources and scripts from the project download section
- Visit our ASYNC group web page at http://www.ics.forth.gr/carvasync