OpenCores

AXI4 to VGA Frame Buffer with Linux driver

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Details

Name: axi_vga_fb
Created: Jan 5, 2017
Updated: Jan 27, 2017
SVN Updated: Jan 27, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Video controller
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This design is very simple in one verilog file.
There is 2 version of the design : RGB332 (one pixel is one byte) and RGB565 (one pixel is 2 bytes)

The block is a slave AXI4 32 bit interface .
Only the 17 or 18 lsbs are taken into account to address 128kByte or 256 kByte of VRAM
each pixel is one byte or 2 bytes and the resolution is 640x200.

The bit mapping for RGB332 is
Blue : 2 bits , bits 7 and 6
Green : 3bits , bits 5, 4 and 3
Red : 3bits , bits 2, 1 and 0

The bit mapping for RGB565 is
Blue : 5 bits , bits 4,3,2,1 and 0.
Green : 6bits , bits 10, 9, 8, 7, 6 and 5
Red : 5bits , bits 15, 14 ,13, 12 , and 11

The VGA signals are made of 4bits for RGB but only the msbs are active, so in RGB565 the colors are truncated and in RGB822 colors are padded.

The VGA timing are those of the 640x480 resolution.
But the logical size is 640x200 , so the lines are repeated twice to occupy 400 (= 2x200) lines on Y axis.

Additionally a C file for linux is provided , it is the driver for frambuffer , it has been tested on linux 3.19 with v586 system.

it should be added inside the linux source inside the ./drivers/video/fbdev region.

The linux driver expects this hardware to be located at 0x40F00000 offset by default but it can be changed inside driver for an other address offset.

About clocking, the input clock is expected to be 100MHz , since the vga RGB output and X/Y counters are updated one cycle out of 4 to mimic a pixel clock of 25.0MHz which is expected for 640x480 VGA timings.

So typically this design is ready to be used with 100MHz systems or 100MHz AXI bus and has been tested on NEXYS 4 DDR board.
if you want to use it with lower bus frequency it may not suitable and with higher bus frequency it should be easily adaptable.