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Details

Name: bcd_adder
Created: Sep 2, 2016
Updated: Jul 25, 2019
SVN Updated: Sep 20, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star5you like it: star it!

Other project properties

Category:Arithmetic core
Language:VHDL
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

The goal of this project is to design a generic BCD adder that can adds two BCD inputs and a carry in to produce a BCD sum and a carry out.