Configurable BCH Encoder and Decoder
Project maintainers
Details
Name: bch_configurable
Created: Mar 28, 2015
Updated: Apr 6, 2015
SVN Updated: Apr 6, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Mar 28, 2015
Updated: Apr 6, 2015
SVN Updated: Apr 6, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties
Category:ECC core
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The project describes an IPCore in verilog about binary BCH encoder and decoder. BCH is a popular error correcting code used in storage and transmission system. It adds some redundancy check data into original data frame, the redundancy data length depends on correcting capacity, and all the calculation proceed in the Galois Field that is suitable for FPGA.
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