OpenCores

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Details

Name: cereon
Created: Sep 30, 2007
Updated: Nov 3, 2007
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
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Bugs: 0 reported / 0 solved
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Other project properties

Category:Uncategorized
Language:VHDL
Development status:
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

Description

[Cereon is a registered trademark of Cybernetic Intelligence, GmbH, Switzerland. The project lead is Andrey Kapustin]

The Cereon architecture addresses the needs of the medium-to-large scale workstations and servers. Hence, the main features of the Cereon architecture include:

• A fully 64-bit architecture, which provides applications with an access to virtually unlimited memory. In the past, there have been some negative experience in getting 64-bit architectures to handle 8-, 16- and 32-bit data efficiently; however, Cereon has been specifically designed to overcome these problems.
• The Cereon instruction set is simple and orthogonal, which allows Cereon processors to be implemented with a very small number of electronic components as compared to other 64-bit architectures currently on the market (aka 16,000 FPGA cells without caches).
• A simple orthogonal RISC instruction set is an ideal target for code generation by compilers.
• As Cereon processors are cheap, it is expected that multi-core and multiprocessor configurations will be commonplace. The Cereon architecture further assists in creating multiprocessor configurations by providing semi-independent I/O and memory access facilities, which reduces the number of conflicts between tasks running on different processors.

The first reference implementation runs (after being directly synthesized from a reference VHDL specification) at over 1.52 DMIPS/MHz in a single-issue in-order variety. It is expected that dual-issue out-of-order Cereon processors will exceed 3 DMIPS/MHz.

Unlike other OpenCores projects, which are mostly either toy or educational, the Cereon core is an industrial-strength core, incorporating caches, JTAC, I/O subsystem, multiprocessing capabilities, performance monitoring features, etc.

A set of tools (assembler, linker, etc) is already available (executables or sources, on demand) for Win32 and Linux platforms. Neither is quite finished; however, both are sufficient to assemble and link a Dhrystone test (as well as an increasing number of architectural tests, which are right now being automated).

All in all, the Cereon processor family is designed to, eventually, force ARM and, maybe even MIPS off the market.

Status

- pre-Alpha