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radix 4 complex fft

## Description

This is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some necessary limited and shift have been done at every butterfly.  
  
A sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the device.  
  

## Features

\- Data width configurable  
\- Point configurable  
\- Input data during data output  
\- Simulation result has compare with Matlab result  

## Status

\- Design is available in VHDL from OpenCores CVS via cvsweb or via cvsget  
\- ...


<h2 id="description">Description</h2>
<p>This is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some necessary limited and shift have been done at every butterfly.<br />
<br />
A sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the device.<br />
<br />
</p>
<h2 id="features">Features</h2>
<p>- Data width configurable<br />
- Point configurable<br />
- Input data during data output<br />
- Simulation result has compare with Matlab result<br />
</p>
<h2 id="status">Status</h2>
<p>- Design is available in VHDL from OpenCores CVS via cvsweb or via cvsget <br />
- ...</p>


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radix 4 complex fft

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