radix 4 complex fft :: Overview

Project maintainers


Name: cfft
Created: Oct 29, 2002
Updated: Feb 14, 2017
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 10 reported / 0 solved
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Other project properties

Category:Arithmetic core
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a


This is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some necessary limited and shift have been done at every butterfly.

A sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the device.


- Data width configurable
- Point configurable
- Input data during data output
- Simulation result has compare with Matlab result


- Design is available in VHDL from OpenCores CVS via cvsweb or via cvsget
- ...

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