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Name: cic_core_2
Created: Aug 16, 2019
Updated: Dec 17, 2019
SVN Updated: Sep 2, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:DSP core
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

CIC filter

It is the CIC filter with Hogenauer pruning. This project is based on project.

Differences are listed below:

  • calculations of pruning with large decimation ratio is improved ;
  • project is rewritten in Verilog and simulated with Icarus;
  • incorrect widths of registers of integrators and combs are fixed;

Getting sarted

  • /rtl/verilog/ - CIC filter decimator
  • /rtl/verilog/cic_functions.vh - functions for calculation parameters of CIC filter
  • /rtl/verilog/ - comb part of CIC filter
  • /rtl/verilog/ - downsampler part of CIC filter
  • /rtl/verilog/ - integrator of CIC filter

  • /sim/rtl_sim/run/ - script to run simulation with Icarus Verilog

  • /sim/rtl_sim/run/cic_d_tb.gtkw - list of signals to watch with GTKWave
  • /sim/rtl_sim/src/ - testbench for CIC filter decimator


Icarus Verilog is used for simulation GTKWave is used for watching the results of simulation

Running the tests

To see simulation results run /sim/rtl_sim/bin/

open output .vcd file with GTKWave load list of signals to watch from cic_d_tb.gtkw


Egor Ibragimov