CIC filter

It is the CIC filter with Hogenauer pruning. This project is based on https://opencores.org/projects/cic_core project.

Differences are listed below:

• calculations of pruning with large decimation ratio is improved ;
• project is rewritten in Verilog and simulated with Icarus;
• incorrect widths of registers of integrators and combs are fixed;

Getting sarted

• /rtl/verilog/cic_d.sv - CIC filter decimator
• /rtl/verilog/cic_functions.vh - functions for calculation parameters of CIC filter
• /rtl/verilog/comb.sv - comb part of CIC filter
• /rtl/verilog/downsampler.sv - downsampler part of CIC filter

• /rtl/verilog/integrator.sv - integrator of CIC filter

• /sim/rtl_sim/run/cic_d_run_sim.sh - script to run simulation with Icarus Verilog

• /sim/rtl_sim/run/cic_d_tb.gtkw - list of signals to watch with GTKWave
• /sim/rtl_sim/src/cic_d_tb.sv - testbench for CIC filter decimator

Prerequisities

Icarus Verilog is used for simulation GTKWave is used for watching the results of simulation

Running the tests

To see simulation results run /sim/rtl_sim/bin/cic_d_run_sim.sh

open output .vcd file with GTKWave load list of signals to watch from cic_d_tb.gtkw

Authors

Egor Ibragimov

Licence

LGPL