small non-pipelined, 3 stage 16-bit cpu (fetch,decode,execute)

Project maintainers


Name: cpu16
Created: Mar 23, 2021
Updated: Mar 29, 2021
SVN Updated: Mar 29, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!

Other project properties

Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL


CPU-16 is a relatively small 16-bit CPU.

It’s a load/store architecture without any pipelining to keep the size done. On an Altera Cyclone it comes in at around 500 LE’s. This goes down to about 400 LE’s if the shifter isn’t dynamic and performs one bit-shift rather than multiple shifts. The size will INCREASE if you use logic elements for the 8x16-bit register bank.

Most instructions take 3 clock cycles, depending on memory speed. There is no wishbone / memory interface but a clock-enable should make this relatively easy. Given a two-clock per instruction per cycle, it’s easy to use block-ram for both ROM- and RAM. For external memory, a dedicated, multi-cycle module can be created.

Both the address- and databus are 16-bit wide. However, accessing bytes will mean that the physical address space goes down to 32Kx16 bits. The CPU allows DMA access by relinquishing the bus after pulling ‘busreq’ high, after which the state-machine will release the bus. Note that the control signals and buses don’t transition to tri-state / hi-z.

This is something that can easily be done by monitoring the busack signal. The core has a single interrupt source and up to 8 (including the external interrupt source) software interrupts that allow for short system calls.

An updated document will be added shortly with the CPU's opcodes and a (rather crappy) assembler..


3/29/2021 Started doc with architecture and instructions

The url of the svn repository is: