cpu65c02_tc - R65C02 Processor Soft Core with accurate timing

I've discovered an infinite loop with the Verilog version when processing the opcode $69. This happens with both iverilog and ModelSim.

Single-stepping with ModelSim shows the code enters the always block at line 5008 of fsm_execution_unit.v, satisfies the condition on line 5994, then loops back to 5008. I think this is due to setting the register zw_ALU (zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} + reg_F0;) as this register also appears in the @always block.

I have only just started learning Verilog, and I have no clue whatsover about VHDL, so my ability to debug this issue is limited.

Closer Investigation will start in the next couple of days.

Thanks for your participation!

Unfortunately, the third party tool to convert VHDL into Verilog I use in the past is not able to generate error-free Verilog files. The design itself was developed on VHDL bases.

The effort to offer both types of source files, VHDL and Verilog, is too high. As the result of this, Verilog sources are no longer available on opencores.org.

May be available again in the future. If anyone need Verilog source urgently and VHDL is unacceptable, please contact me directly.