cpu65c02_tc - R65C02 Processor Soft Core with accurate timing

Description

The 65C02 by Rockwell is the upgraded version of the legendary Rockwell's R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the R65C02. This soft core was generated in VHDL and was designed with Mentor's HDL Designer.
It comes also with graphical views formatted in HTML to show and explain very clearly the hierarchy of the whole design.

Please feel free to tell me any ideas, errors or some thing else like special functions, test benches or documentation. Use the "Tracker" link to do this.

Features

- Two variants: BASE - v1.53 / traditional coding and v2.00 / performance improvements HIGH SPEED - fmax typically 110 MHz up to 180 MHz for low/middle cost FPGA devices ('released' SECTION, 'rtl/v2_00/')
- true cycle timing for all official opcodes
- unknown op's decoded as "NOP/special op codes"
- one clock source
- input signal "rdy_i" for generating waitstates (see attached specification of R65C02)
- output signal "sync_o" to indicate an op fetch (see attached specification of R65C02)
- input signal "so_n_i" sets the internal OV Flag (see attached specification of R65C02)
- fully synthesizable VHDL

Status

- This version supports Rockwell's 65C02 original software
- Core is running in a APPLE //e SoC and tested under ProDOS V2.0.3
- "PASSED" Klaus Dormann's 6502/65c02 test suite (functional, extended & interrupts) written in assembler (included in /asm)
- "PASSED" Bruce Clark's decimal tests written in assembler (included in /asm)
- Added "beta" section to separate upcoming releases from currently released versions. The released version moved to "released"
CORE: "READY - PRODUCTION"
LICENSE: Puplished under GPL V3
DOCUMENTATION: "ready"
TESTBENCHES: "ready"
TESTSOFTWARE: "ready"

QUALITY:
- all of the new R65C02 op codes are tested under real working conditions and software testbenches
- Interrupts in R65C02 like order: BRK - NMI - IRQ

History

Feb-19-2021
SECTION "released":
Revision 1.53 2021/01/08 22:20:00 jens "BASE"
Revision 2.00 2021/01/22 13:27:00 jens "HIGH SPEED"
- Dividing the root core into "BASE" and "HIGH SPEED"

Oct-14-2018
SECTION "beta":
Revision 2.00RC 2018/10/14 11:50:00 jens
- Performance improvements

Sep-10-2018
Revision 1.52 2018/09/10 12:14:00 jens
- RESET generates SYNC now, 1 dead cycle delayed

Revision 1.52 RC 2018/09/09 03:00:00 (RELEASE CANDIDATE)
- ADC / SBC flags and A like R65C02 now

Revision 1.52 BETA 2018/09/05 19:35:00
(never submitted to opencores)
- BBRx/BBSx internal cycles like real 65C02 now
- Bug Fix ADC and SBC in decimal mode (all op codes -
1 cycle is missing
- Bug Fix ADC and SBC in decimal mode (all op codes -
"Overflow" flag was computed wrong)

Revision 1.52 BETA 2018/09/02 18:49:00
(never submitted to opencores)
- Interrupt NMI and IRQ processing via FETCH stage now

Revision 1.52 BETA 2018/08/30 15:39:00
(never submitted to opencores)
- Interrupt priority order is now: BRQ - NMI - IRQ
- Performance improvements on-going (Mealy -> Moore)

Revision 1.52 BETA 2018/08/23 20:27:00
(never submitted to opencores)
- Bug Fixes All Branch Instructions
(BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA)
3 cycles now if branch forward occur and the branch
instruction lies on a xxFEh location.
(BBR, BBS) 6 cycles now if branch forward occur and the
branch instruction lies on a xxFDh location.
- Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now
- Bug Fix Now all cycles are delayable (WR and internal)

Revision 1.51 RC 2014/04/19 14:44:00
(never submitted to opencores)
- Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH.
When the ABS address data bytes cross the page
boundary (e.g. $02FE JMP hhll reads hh from
$02FF and ll from $0200, instead $02FF and $0300)

Aug-02-2013
Revision 1.5 RC 2013/07/31 11:53:00 (RELEASE CANDIDATE)
- Bug Fix CMP (IND) - wrongly decoded as function AND
- Bug Fix BRK should clear decimal flag in P Reg
- Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address
- Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created
- Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong)
- Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed
- Bug Fix RTI - should increment stack pointer
- Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.
- Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong)
- Bug Fix RMB, SMB Bug - Bit position decoded wrong
Revision 1.4 2013/07/21 11:11:00 (internal copy only - not published)
- Changing the title block and internal revision history
- Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)

Feb-25-2009
- Correct "RTI" (wrong: use of stack pointer)
- Correct "RMBx" & "SMBx" (wrong: bit translation)
- Rename all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- Correct timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- Optimize end states of "STA" (s197,s207,s200,s213)

Jan-04-2009
- Deleted unused/duplicated nets, registers and modules. Renamed some blocks. Synthesis run now without warnings.

Dec-01-2008
- CVS loaded with updated finite state machine (bug fixes for interrupts)
- Include an example for specification (copied from cpu6502_tc - on working)

Aug-05-2008
- CVS loaded with BETA source files (VHDL)