Feb 19, 2021 | v2.00 PRODUCTION HIGH SPEED variant and v1.53 PRODUCTION released | Gutschmidt, Jens |
Oct 14, 2018 | Upcoming v2.00rc PERFORMANCE IMPROVEMENTS - fmax is now typical from 110 MHz to 180 MHz even for low/middle cost FPGA devices. High End FPGA devices allow clock rates over 250 MHz now. | Gutschmidt, Jens |
Sep 10, 2018 | v1.52 PRODUCTION released | Gutschmidt, Jens |
Sep 10, 2018 | RESET generates SYNC now, 1 dead cycle delayed | Gutschmidt, Jens |
Sep 9, 2018 | RC v1.52 available - Fix cycle counts in branches & INT, fixes in JMP, ADC, SBC | Gutschmidt, Jens |
Aug 2, 2013 | "BETA" changed to "RELEASE CANDIDATE" with major bug fixes - all op codes tested now | Gutschmidt, Jens |
Mar 15, 2010 | Updated HTML of project status - BUG FIX for NMI & IRQ comes at a later time | Gutschmidt, Jens |
Feb 25, 2009 | BUG FIX "RTI" (wrong: use of stack pointer)
CORRECT "RMBx" & "SMBx" (wrong: bit translation)
CORRECT timing for addressing mode "ABS,X" for "INC" | Gutschmidt, Jens |
Jan 4, 2009 | Changes commited to CVS | Gutschmidt, Jens |
Jan 4, 2009 | Updated BETA release - Removed unused nets, registers and modules. Updated documentation. | Gutschmidt, Jens |
Dec 1, 2008 | BUGS fixed - Please check "Tracker -> "Bugs" | Gutschmidt, Jens |
Aug 13, 2008 | BUGS found - Please check "Tracker" -> "Bugs" | Gutschmidt, Jens |
Aug 5, 2008 | Loading source files "rtl" up to the CVS. STATE=BETA | Gutschmidt, Jens |
Apr 12, 2008 | Project started | Admin, OpenCores |