OpenCores

cpu65c02_tc - R65C02 Processor Soft Core with accurate timing

Issue List
Branch takes incorrect number of cycles #9
Closed hoglet opened this issue over 6 years ago
hoglet commented over 6 years ago

Hi Jens,

Are you still interested in bug reports for the 65C02 True Cycle core?

Here is bug 2 of 3:

I've been debugging the JMP page crossing bug with my 6502 Bus Analyzer. This will flag errors where it spots a behaviour that is inconsistent with it's own internal model of the 65C02.

It flagged the following branch as having the wrong number of cycles:

2EFB : 6A : ROR A : 2 : A=4C X=00 Y=A3 SP=F7 N=0 V=1 D=0 I=0 Z=0 C=1 0 66 1 1 1 19 0 1 2 0c 0 1 3 0c 0 1 4 86 0 0 2EFC : 66 19 : ROR 19 : 5 : A=4C X=00 Y=A3 SP=F7 N=1 V=1 D=0 I=0 Z=0 C=0 0 90 1 1 1 02 0 1 2 65 0 1 3 4d 0 1 2EFE : 90 02 : BCC 2F02 : 4 : A=4C X=00 Y=A3 SP=F7 N=1 V=1 D=0 I=0 Z=0 C=0 0 6a 1 1 1 6a 0 1 2F02 : 6A : ROR A : 2 : A=26 X=00 Y=A3 SP=F7 N=0 V=1 D=0 I=0 Z=0 C=0

My understanding is a branch incurs the extra page crossing cycle if the target is on a different page than the instruction AFTER the branch instruction. So a branch at xxFE should only take three cycles.

Many thanks again for your excellent core!

Dave (hoglet on 6502.org and stardot.org.uk)

biged commented over 6 years ago

Here's a couple of visual6502 simulations to illustrate:

This branch: http://visual6502.org/JSSim/expert.html?graphics=false&steps=10&r=fe&a=fe&d=9002eaeaeaea is just 3 cycles, but the same branch one byte lower in memory hits the page crossing: http://visual6502.org/JSSim/expert.html?graphics=false&steps=10&r=fd&a=fd&d=9002eaeaeaea

fpga_is_funny commented over 6 years ago

Hi Dave and Ed

Both are right.

All branch instructions for 6502_tc AND 65c02_tc (+ BBRx&BBSx) are effected if branch occur under following condition: -> 2EFEh 90h 02h BCC 2F02h (2nd cyc. = 2EFFh, 3rd cyc. = 2F00) 2F00h (...) 2F02h 8Ah ROR A 4 cycles instead of expected 3

2EFF 90h xxh is correctly decoded.

Little effort to fix this. The page cross event is wrongly marked at 2nd cycle while decoding (reading in offset byte). Must be marked at 3rd cycle (dummy cycle, PC point to the next instruction follows the branch instruction) instead. Will be fixed in the next upcoming release for 6502_tc AND 65c02_tc.

Please take a look at my comment for actual bug "JMP..." for general info.

Thanks to all for the good job, their comments and fine documentation.

fpga_is_funny closed this about 6 years ago

Assignee
No one
Labels
Request