A. Moore, Scott

8080 Compatible CPU

These versions of the design have a typo in the STAX instruction:


> if (opcode[4]) // use DE pair
>                         waddrhold <= regfil[`reg_d]<<8|regfil[`reg_d];

reg_d is used twice.

Typo in m8080.v and sm8080.v

hello?I download your code for study?I doubt the RST instructions in your cpu8080.v?line 1008~1010 ?have a problem?as follow?

     if (intcyc) { wdatahold2, wdatahold } <= pc;
        else { wdatahold2, wdatahold } <= pc+16'h3;
    { wdatahold2, wdatahold } <= pc+16'h1; // of address after call

I think you should modify as follow?
    
       if (intcyc) { wdatahold2, wdatahold } <= pc;
        else { wdatahold2, wdatahold } <= pc+16'h1; // of address after call

RST instruction

On line 717 of cpu8080/tags/update/project/cpu8080.v there is:

6'b110000, 6'b110000: begin

The context is:

    714                   // the illegal opcodes behave as NOPs
    715
    716                   6'b001000, 6'b010000, 6'b011000, 6'b100000, 6'b101000,
    717                   6'b110000, 6'b110000: begin
    718
    719                      state <= `cpus_fetchi; // fetch next instruction
    720                      pc <= pc+16'h1; // Next instruction byte
    721
    722                   end


Is the duplicated entry for 6'b110000 intended?

redundant case item 6'b110000

hi
m doing the same project as u but its very large..
it is 64 bit cpu.
in verilog i am making 64 bit double precision cpu.
if u know anything about this den pls help me out
u can send it to my id:
swapna6688@gmail.com
pls
thank u

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8080 Compatible CPU