SoC Debug Interface

Description

Debug Interface is used for development purposes (debugging). It is an interface between the CPU(s), peripheral cores and any commercial debugger/emulator. The external debugger or BS tester connects to the core via JTAG port that is fully IEEE 1149.1 compatible. For that reason jtag TAP needs to be used together with this core.

Status

- New version tested with a test bench and in real HW. (April 8, 2004)
- Old debug (development) was separated into two different projects. Debug interface is rewritten, documentation updated. Use rel_22 tag for downloading. [January 27, 2004]
- All files were updated [February 4, 2002]
- Development Interface was thoroughly tested (functional simulation and in real hardware).
- GDB debugger was connected to the Development Interface.
- Boundary Scan is supported. BS chain of the chip where Debug Interface is used, must be defined prior to its use.
- Specification is finished: DbgSupp.pdf (about 200 KB) (see Downloads).
- Datasheet is ready: Debug Support Datasheet (prl.).pdf (see Downloads).

Change log

- 08/04/2004 IM New version. Use rel_25 tag for downloading. Documentation updated.
- 17/01/2004 IM New version. Use rel_22 tag for downloading. Documentation updated.
- 12/02/2002 IM Datasheet written.
- 04/02/2002 IM Documentation and code updated (small fixes to make the core smaller, faster and of course more stable).
- 04/12/2001 IM Documentation and code updated (small fixes, wishbone master interface added)
- 20/9/2001 IM Documentation and code updated (final release)
- 13/9/2001 IM Documentation and code updated
- 23/5/2001 IM Documentation updated
- 8/5/2001 IM Initial web page + first check-in

Feel free to send me comments, suggestions and bug reports.