Double Clocked FFT Core

Modelsim simulation output is all X's with valid inputs. Imaginary part periodically - every 256 clocks - outputs all 0's. It seems to work correctly in an FPGA though. There's probably something not being reset or initialized in the source.

fftgen -f 512 -n 14 -k1 -p 100 -dir fft-core_f512_n14_k1_p100

Inserting: initial idle = 0; in fftstage.v after line 200, seems to fix the issue.

Which makes idle 0, rather than X. I believe always @ ( * ) automatically builds the sensitivity list - which in this case is empty - rather than the sensitivity list being all signals.

To do this, insert: "\t\tinitial idle = 0;\n" in bldstage.cpp after line 503.