Created: Feb 21, 2015
Updated: Apr 7, 2018
SVN Updated: Jul 2, 2018
Latest version: download
(might take a bit to start...)
2 reported / 2 solved
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The goal of this project is to create an IP core for an FFT that runs, in a pipelined fashion, at two samples per clock. A C++ program will generate the Verilog files, allowing the FFT to be of an arbitrary length--subject only to the capability of the FPGA used to implement the FFT.
One of my goals is to create an FFT core that can be used with open source and third party Verilog simulation facilities, such as Verilator. This would be difficult with a proprietary IP core.
For those who might be wondering, why would I need an FFT that runs at two samples per clock? Let me remind them that FFT's tend to use their multiplies more efficiently than other filtering implementations, but to do so you need to use some form of overlap and add filtering structure. An overlap and add structure immediately puts you into needing an FFT that runs at twice the clock speed of the incoming data.
The following statistics come from a Basys-3 development board implementation using Vivado as the development tool:
|Twiddle Factor Bits||17||17||17||17||17||17|
|Extra Internal Bits||1||1||1||1||1||1|
|Stages with Optimized Multiplies||3||4||5||6||7||7|
|Flip Flop Pairs||3622||4625||5469||6389||7577||12223|
I should also note that the last two stages of any of these FFT implementations don't use multiplies, just adds and subtracts. As a result seven stages of hardware multiplies is the maximum you can have for a 512 point FFT. The 1024 point FFT does one multiply stage in logic, and the result is ... expensive.
If I can muster the time to keep working on this, I'd like to add ...
* A capability to do FFT's on real samples, rather than just complex
* A capability to operate at one sample per clock, or even one sample every two clocks
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